Excavating
Patent
1996-10-29
1997-12-23
Canney, Vincent P.
Excavating
39518301, G06F 1100
Patent
active
057013080
ABSTRACT:
A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.
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Attaway Brett W.
Kelley H. Ray
Lofgren John D.
Canney Vincent P.
Lockheed Martin Corporation
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