Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
1998-01-06
2001-10-02
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S208100, C257S292000
Reexamination Certificate
active
06297492
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to imaging devices. In particular, the present invention relates to devices that detect and provide a measure of an intensity of light impinging on imaging pixels in an array.
(2) Background Information
Imaging arrays are frequently used to produce an image representing an object. The imaging arrays typically include rows and columns (bitlines) of photo detectors (pixels). Imaging arrays may also be uni-dimensional, including one row of photo detectors. Such imaging arrays are used in document scanners. The photo detectors generate photo charges proportional to light reflected from an object to be imaged. Photo charges from each pixel are converted to a signal (charge signal) or potential representative of a level of energy reflected from a respective portion of the object. The signal or potential is read and processed by video processing circuitry to create an image representing an object.
Pixels belongings to a same bitline are usually connected at a common output node from where a signal or potential, representative of the level of energy, is read out. Pixels belonging to the same bitline “see” an overall capacitance (hereinafter referred to as “bitline capacitance”), at the common output node. Each pixel in a same bitline is individually controlled to read out at the common output node. Typically, pixels belonging to a same row are commonly controlled by a same signal such that an entire row may be read out at a substantially same time.
Improvement in the speed at which rows of pixels are read out, without substantially negatively affecting bitline swing, constitutes a constant challenge for circuit designers. To reduce overall cost in image sensor devices, it has become desirable and possible to integrate image sensor arrays with digital circuitry that controls the operation of the array and processes the array's output. Integration of an image sensor with complementary-metal-oxide-semiconductor (CMOS) support circuitry is most desirable because of the low power consumption characteristics and common availability of CMOS technology. Such an imaging array integrated with CMOS support circuitry is called CMOS active pixel sensor (APS) array.
Typically, a pixel cell includes a driving device that receives an electronic signal indicative of an intensity of light detected by the image sensor and drives a current proportional to the measure of intensity, to a bitline to which the pixel cell is coupled. Following signal integration, pixels of a selected row are accessed by asserting a WORDLINE signal to each pixel access device of each pixel cell of the selected row. Then the bitlines, to which the pixel cells of a same selected row are coupled, may be charged by a current driven by a driver device of the pixel cells of the selected row, to a voltage level V
out
representative of an intensity of light detected by the pixel cells of the selected row. The pixels of an entire row may thus be read out at a substantially same time. The pixel cells of other rows, not currently accessed, have their pixel access devices switched off by a deasserted WORDLINE signal corresponding to these rows.
The CMOS support circuitry of the CMOS active pixel sensor array introduces a relatively high capacitance (source-drain) to the bitline that is charged at read out time. This capacitance slows down the read out process. Moreover, MOS transistors display the “body effect” according to which the threshold voltage V
TH
raises with a raise in the voltage difference (V
SB
) between the bulk and the source. This is reflected in the formula V
TH
=V
TO
+&Ggr;({square root over (|−2+L &PHgr;
F
+L +V
SB
+L |)}−{square root over (2+L |&PHgr;
F
+L |)}). According to this formula, when V
SB
≠0, V
TH
increases with V
SB
. In this formula, V
TO
is the threshold voltage when V
SB
=0, parameter &Ggr; (gamma) is termed the body effect coefficient or body factor, and the function |
F
is termed equilibrium electrostatic potential in the semiconductor of the transistor. Since V
TH
raises with V
SB
and V
SB
is proportional to V
out
, V
TH
raises with V
out
, where V
out
is the voltage read out. For a MOS transistor V
out
=V
in
−V
TH
, where V
in
is the voltage applied to a gate of the MOS transistor. Thus when a MOS transistor is placed at the output of a read out circuit, as in a CMOS source-follower circuit typically used in CMOS active pixel sensor arrays, the voltage read out V
out
does not depend linearly with V
in
. Also, the output range of the read out circuit is decreased by the variation of V
TH
with V
out
, such variation causing degradation of the output's dynamic range.
It is desirable to minimize the capacitance “seen” at the output of the read out circuit. It is also desirable to provide an apparatus and method for reading out a CMOS active pixel sensor array with improved read out speed and no degradation of the output's dynamic range.
SUMMARY OF THE INVENTION
The present invention provides a read out circuit. The read out circuit includes an emitter follower circuit (EFC) that receives information indicative of an intensity of light detected by a pixel of an active pixel sensor array. The EFC drives a value, related to the information, to a read out device when the pixel is accessed.
REFERENCES:
patent: 4274113 (1981-06-01), Ohba et al.
patent: 5283428 (1994-02-01), Morishita et al.
patent: 5471515 (1995-11-01), Fossum et al.
patent: 5541402 (1996-07-01), Ackland et al.
patent: 5552832 (1996-09-01), Astle
patent: 5602585 (1997-02-01), Dickinson et al.
patent: 5614744 (1997-03-01), Merrill
patent: 5869857 (1999-02-01), Chen
patent: 5933188 (1999-08-01), Shinohara et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Que T.
Luu Thanh X.
LandOfFree
Fast BICMOS active-pixel sensor cell with fast NPN... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast BICMOS active-pixel sensor cell with fast NPN..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast BICMOS active-pixel sensor cell with fast NPN... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2575928