Fast array multiplier

Details Fast array multiplier Fast array multiplier

1996-12-02

1999-10-26

Moise, Emmanuel L.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708625, 708627, G06F 752

Patent

active

059744375

ABSTRACT:
A number of adder structures (also referred to herein as "tiles" and "Quickadders.TM.") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs and which may be placed so as to span one or more bitslices of a multiplier array. In a second aspect of the present invention, groups of replicable circuitry columns are provided for forming multiplier arrays for multiplying binary numbers X and Y to obtain a binary product Z. These groups of columns of circuitry include left column groups to handle X-inputs to the array, internal column groups, and right column groups to handle outputs to a CLA adder/subtractor (or equivalent) for processing the MSBs of the product. The LSBs of the product are produced directly by the array. The groups may be thought of as replacing 2, 3 or 4 conventional columns of full-adder circuitry of a basic array such as that shown in FIGS. 1 and 2. The new groups of columns significantly speed up the process of multiplication through use of rewiring techniques and the use of Fc, Fo, Fx, Fw, Fz, Fv, Fu and/or Fy-type Quickadders.TM. and associated circuitry.

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