Boots – shoes – and leggings
Patent
1992-10-30
1994-01-11
Mai, Tan V.
Boots, shoes, and leggings
G06F 750
Patent
active
052787834
ABSTRACT:
A carry look-ahead adder obtains high speed with minimum gate fan-in and a regular array of area-efficient logic cells in a datapath by including a first row of propagate-generate bit cells, a second row of block-propagate bit cells generating a hierarchy of block-propagate and block-generate bits, a third row of carry bit cells: and a bottom level of sum bit cells. The second row of block-propagate bit cells supply the block-propagate and block-generate bits to the first carry bit cells in chained segments of carry bit cells. In a preferred embodiment for a 32-bit complementary metal-oxide semiconductor (CMOS) adder, the logic gates are limited to a fan-in of three, and the block-propagate bit cells in the second row are interconnected to form two binary trees, each including fifteen cells, and the carry cells are chained in segments including up to four cells. In general, the interconnections between the block-propagate bit cells are derived from a graph which is optimized to meet the constraints of fast static complementary metal-oxide-semiconductor (CMOS) circuit design: low fan-out and small capacitance load on most signals. Sufficient gain stages are present in the binary trees to build-up to a large drive capability where the large drive capability is needed.
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Cefalo Albert P.
Digital Equipment Corporation
Hudgens Ronald C.
Mai Tan V.
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