Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-09-12
2004-10-12
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S428000, C370S471000, C370S474000
Reexamination Certificate
active
06804240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet processing device and a packet processing method for carrying out packet processing.
2. Description of the Background Art
In recent years, in conjunction with the drastic increase of traffic on the Internet, there are increasing demands for a device capable of realizing fast processing of packets that transfer information on the Internet. The packet processing is realized by referring to a header portion of a packet entered from the external, and carrying out a desired processing according to information described in that header portion.
Here, the desired processing can be any of the various processings including the following, for example.
(1) A processing for transferring a packet to a specific output link by referring to a destination address contained in the header portion of the packet.
(2) A processing for controlling a packet transfer timing at each output link by referring to priority level information or information indicating attributes of an application that is:carrying out communications using the packet, that is contained in the header portion of this packet, such that the transfer of this packet is paused when a packet with a higher priority level is transferred to an output link to which this packet is to be transferred, for example.
(3) A processing for dividing the packet according to a prescribed method in the case where its packet length exceeds the maximum packet length permitted at a specific output port.
(4) A processing for incrementing a specific information on the packet and discarding the packet when this specific information reaches to a prescribed value.
(5) A processing for rewriting a value of a destination address or a source address according to a prescribed method, according to the need.
(6) A processing for calculating error correction codes of the packet, according to the need.
Historically speaking, a device for processing packets has been realized by an information processing device such as a mini-computer or a micro-processor. In this case, the specific processing to be carried out for each packet as described above is realized by executing a specific instruction sequence at the mini-computer or the micro-processor. However, in this scheme it has been difficult to realize the fast packet processing. For this reason, it is customary in recent years to realize the fast packet processing by implementing the packet processing using hardware.
However, the Internet protocol has a characteristic of being changed continually. For example, the destination address and the source address in the packet have not been subjected to rewriting inside the Internet until a few years ago, but as a resolution to the shortage of the IP addresses due to the Internet boom of the recent years, it has become customary in last two or three years to rewrite the destination address or the source address inside the Internet.
As such, the Internet is operated in such a way that whenever a problem arises while operating the network, a protocol is changed to resolve that problem. As a result, the Internet protocol will continue to change. Consequently, the above described scheme for realizing the fast packet processing by implementing the protocol processing using hardware has a problem in that it becomes impossible to carry out the processing by that hardware even when there are only minor changes in the protocol, and therefore it becomes necessary to replace the packet processing device very frequently.
Also, there have been various propositions for schemes to realize functions required for the packet processing, such as a processing for analyzing the destination address in the header of the IP packet, for example, but in view of different advantages of different function realization schemes, each function realization method has its preferred area for its application. However, the prior art packet processing device has not been provided with a way to select an appropriate scheme from these plurality of function realization schemes easily, and only one particular scheme selected from the various packet processing schemes has been implemented in the prior art packet processing device. As a result, it has been impossible to select the optimum scheme depending on the network environment such as a mixture rate of different packet types, for example, so that it has been impossible to carry out the packet processing efficiently.
As described, the prior art packet processing device has been associated with the problems including: (1) that it is difficult to realize the fast processing when the device is realized by executing a specific instruction sequence at the mini-computer or the micro-processor; (2) that it cannot deal with the protocol change flexibly when the device is realized by implementing the packet processing using hardware; and (3) that it cannot select an optimum function realization scheme depending on the network environment.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a packet processing device and a packet processing method capable of realizing a fast packet processing, a high adaptability with respect to the protocol change, and an ability to select an optimum function realization scheme according to the network environment.
According to one aspect of the present invention there is provided a packet processing device, comprising: a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit; wherein the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.
According to another aspect of the present invention there is provided a packet processing method, comprising the steps of: (a) extracting a plurality of prescribed bit sequences from an input packet, and generating a digest information capable of specifying at least a part-of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and (b) processing the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the step (a); wherein the step (a) generates the digest information with respect to a next input packet while the step (b) carries out a processing for one packet.
Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
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Okamoto Toshio
Shimojo Yoshimitsu
Shirakawa Kenji
Shobatake Yasuro
Kizou Hassan
Levitan Dmitry
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