Fast address latch with automatic address incrementing

Details Fast address latch with automatic address incrementing Fast address latch with automatic address incrementing

1993-12-30

1996-05-21

Harvey, Jack B.

395310, 395403, G06F 13364

Patent

active

055198724

ABSTRACT:
A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.

REFERENCES:
patent: 4107786 (1978-08-01), Masaki et al.
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 4926312 (1990-05-01), Nukiyama
patent: 5014188 (1991-05-01), Kawamura
patent: 5157776 (1992-10-01), Foster
patent: 5235545 (1993-08-01), McLaury
patent: 5253348 (1993-10-01), Scalise
patent: 5287481 (1994-02-01), Lin
patent: 5333293 (1994-07-01), Bonella
patent: 5375079 (1994-12-01), Uramoto et al.
patent: 5379384 (1995-01-01), Solomon
patent: 5388133 (1995-02-01), Vijen et al.
patent: 5450460 (1995-09-01), Stodieck

Affiliated with

Also associated with

Rating

Fast address latch with automatic address incrementing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast address latch with automatic address incrementing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast address latch with automatic address incrementing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2047203