Fast adder/subtractor for signed floating point numbers

Details Fast adder/subtractor for signed floating point numbers Fast adder/subtractor for signed floating point numbers

1998-02-06

2001-01-16

Ngo, Chuong Dinh (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06175851

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system and method for performing floating point calculations, and more particularly, to a circuit for adding or subtracting signed floating point numbers.
BACKGROUND OF THE INVENTION
Digital circuits and methods for performing arithmetic operations on signed floating point numbers are well known in electrical engineering and are used in numerous applications ranging from computer graphics to scientific calculation. Herein, IEEE and/or IEEE-compatible floating point numbers are considered, which comprise a sign bit, an exponent portion, and a mantissa portion. Each aforementioned portion is represented by a particular number of bits, in a manner well understood by those skilled in the art.
FIG. 1
is a flowchart showing steps typically employed by conventional floating point adder/subtractor logic. Conventional techniques for adding or subtracting two numbers in IEEE floating point notation usually require an alignment of the mantissas so that both numbers' exponents are rendered equal prior to the operation. This is typically accomplished by first comparing and determining the exponential difference between the two numbers, and then shifting the mantissa of the smaller number to the right until the exponents are equal.
When a floating point operation corresponding to an absolute subtraction is to be performed, two's complement is applied to the mantissa of number to be subtracted. The two mantissas are then added together, and, if necessary, two's complement is applied to the result to ensure that the resulting magnitude is in absolute terms.
Those skilled in the art will recognize that the operations shown in
FIG. 1
do not produce a normalized floating point number. Thus, additional steps are required to convert the number into normalized IEEE floating point notation. Additional steps are also required to handle special results such as Not-a-Number (NaN), infinity, or overflow. Such additional steps are well known, and are therefore not considered herein.
As shown in
FIG. 1
, conventional floating point adder/subtractor logic typically employs six serial steps. The performance of these steps in serial increases both the latency and the cost of conventional adder/subtractor logic. Assuming that each serial step requires a fixed amount of time, then completion of all six serial steps would require six times this fixed amount of time, regardless of the details of the logic used to implement the individual serial steps. As a result, a finite boundary is placed on the speed capabilities of conventional floating point adder/subtractors.
Conventional adder/subtractor logic also undesirably requires the implementation of at least two sets of two's complement logic. Two's complement logic is relatively expensive since each two's complement that is performed requires increment and carry logic.
Therefore, there remains a need for a high speed circuit for adding and subtracting signed floating point numbers that reduces the number of required sequential steps and simultaneously reduces cost.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies and limitations of the prior art with a novel system of adding or subtracting signed floating point numbers. The system of the present invention advantageously performs a comparison of two signed floating point inputs in parallel with a single bit shift, an exponential difference and a one's complement computation on both inputs. Performing the comparison, single bit shift, exponential difference and one's complement computation in parallel advantageously reduces the number of sequential steps required to add or subtract the signed floating point number inputs. The comparison also eliminates the need for additional hardware necessary to perform two's complement for subtractions. Moreover, the system advantageously combines a two's complement computation with an additional step by using a single bit as a carry-in (or rounding) to an adder. As a result, the present invention significantly increases the overall speed and efficiency of the system while simultaneously reducing cost.
A fast adder/subtractor for signed floating point numbers constructed in accordance with the present invention includes a comparator and a selector. The comparator is coupled to receive a mantissa portion and an exponent portion of a first signed floating point number and a mantissa portion and an exponent portion of a second signed floating point number and is used to determine which of the signed floating point number has a greater magnitude. The selector is coupled to receive the mantissa portions of the first and second signed floating point numbers and is used to select the appropriate mantissa portions of both numbers for the operation. More specifically, the selector is coupled to receive a one's complement of the mantissa portion of both numbers, the mantissa portion of both numbers right shifted by one bit, a one's complement of the mantissa portion of both numbers right shifted by one bit, and the mantissa portion of both numbers right shifted by two bits. A fast adder/subtractor for signed floating point numbers embodying the principles of the present invention further includes an absolute addition signal circuit, for indicating whether an absolute addition or an absolute subtraction is to be performed; a single-bit shift circuit, for indicating whether at least a single bit shift is to be performed; a remaining shift count circuit, for determining an amount by which the mantissa portion of the lesser of the two signed floating point number inputs needs to be shifted further; and an adder, for producing a resulting mantissa portion.
The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specifications, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes.


REFERENCES:
patent: 5122981 (1992-06-01), Taniguchi
patent: 5146419 (1992-09-01), Miyoshi et al.
patent: 5282156 (1994-01-01), Miyoshi et al.
patent: 5627773 (1997-05-01), Wolrich et al.
patent: 5684729 (1997-11-01), Yamada et al.

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