Fast adder chain

Details Fast adder chain Fast adder chain

1994-09-21

1996-08-06

Mai, Tan V.

Boots, shoes, and leggings

G06F 750

Patent

active

055440851

ABSTRACT:
A fast adder chain for adding together at least one pair of digital words and including a plurality of cascaded adder blocks. Each block having computation adders for obtaining the pseudosum of said pair of digital words and latches for storing and transmitting the pseudosum to the next block and the pseudocarry from the computation to the chain end.

REFERENCES:
patent: 3925651 (1975-12-01), Miller
patent: 5113362 (1992-05-01), Harston et al.
IEEE Proceedings G. Electronic Circuits & Systems, vol 133, No. 5, Oct. 1986, Stevenage GB, pp. 256-264, H. Yung et al., "Recursive Addition and Its Parameterisation in VSLI".
Proceedings of the 1990 IEEE International Symposium on Circuits and Systems, 1-3 May, 1990, New Orleans, LA, USA, vol. 2, IEEE, New York, USA, pp. 982-986, T. Noll, "Carry-Save Arithmetic for High-Speed Digital Signal Processing".
IEEE Journal of Solid State Circuits, vol. 23, No. 2, Apr. 1988, New York, US, pp. 573-580, C. Ekroot, "A GaAs 4-Bit Adder-Accumulator Circuit for Direct Digital Synthesis".
Beraud et al., "High speed Accumulator", IBM Tech. Discl. Bull. vol. 17, No. 1, Jun. 1974, pp. 118-119.
Clocksin, "Automatic Specialisation of Standard Design", Computer Journal, vol. 29, No. 6, Dec. 1986, London GB, pp. 495-499.
Kwang, "Computer Arithmetic", Wiley & Sons, New York, US., 1979, pp. 40-43.

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