Fast acquisition bit timing loop method and apparatus

Details Fast acquisition bit timing loop method and apparatus Fast acquisition bit timing loop method and apparatus

1995-07-31

1997-08-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

H04L 700

Patent

active

056549911

ABSTRACT:
In a direct sequence spread spectrum receiver, an apparatus for obtaining and adjusting bit synchronization. In one aspect, the bit synchronization is adjusted by selectively inverting a clocking circuit to delay sampling by one-half a clock cycle and to combine the inversion with a skipping of one cycle to advance the sampling by one-half cycle. In another aspect of the invention, the synchronization circuit avoids overflow of accumulating components by downshifting both the partial sums and the input data when needed.

REFERENCES:
patent: 4805191 (1989-02-01), Burch et al.
patent: 5402448 (1995-03-01), Marko et al.
patent: 5499273 (1996-03-01), Kull et al.

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