Fast accessible semiconductor memory device

Details Fast accessible semiconductor memory device Fast accessible semiconductor memory device

2001-10-15

2003-11-11

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S051000

Reexamination Certificate

active

06646946

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an arrangement of a memory array readily allowing expansion of a data bit width and enabling fast data access.
2. Description of the Background Art
FIG. 52
is a diagram schematically showing an arrangement of an array mat of a conventional semiconductor memory device (a DRAM: a Dynamic Random Access Memory) having 64-M bit storage capacity. Referring to
FIG. 52
, a semiconductor memory device CH includes four memory mats MTa to MTd each having 16-M bit storage capacity. Peripheral circuits PHa to PHc each are arranged in a central region among memory mats MTa to MTd. Peripheral circuit PHa includes a circuit for controlling an access operation for memory mats MTa to MTd. Peripheral circuits PHb and PHc include a data input/output circuit and an external signal input circuit for producing an internal signal for peripheral circuit PHa.
As shown in
FIG. 52
, the memory array is so divided into four memory mats MTa to MTt as to reduce the lengths of word and bit lines respectively arranged corresponding to a row of and a column of memory cells, thereby enabling memory cell selection operation at high speed.
FIG. 53
is a diagram showing an arrangement of memory mats MTa to MTd shown in FIG.
52
. One memory mat MT is shown in FIG.
53
. As shown in
FIG. 53
, memory mat MT is divided into sixteen memory sub blocks MSB by word line shunt regions WS in a row direction, and also divided into thirty-two memory sub blocks MSB by sense amplifier bands SAB in a column direction. A column selection line CSL is provided extending from a column decoder CD arranged on one side of memory mat MT in the column direction, and shared by memory sub blocks MSB aligned in the column direction. A column selection signal from column decoder CD is transmitted onto column selection line CSL. Here, the word line shunt region corresponds to a region where a gate electrode layer formed of a material having a relatively high resistance such as polysilicon and having the memory cells connected thereto, and a low resistance conductive layer provided above the gate electrode layer and formed, for example, of aluminum are electrically connected. By connecting the upper low resistance conductive layer and the lower gate electrode layer in word line shunt region WS, a resistance of the word line is equivalently reduced. Sense amplifier band SAB includes sense amplifier circuits arranged corresponding to the columns of memory sub blocks MSB for sensing, amplifying and latching memory cell data of corresponding columns when activated.
Memory mat MT is divided into 16·32=512 memory sub blocks MSB. Memory sub blocks MSB includes 32K memory cells arranged in 256 rows 128 columns. By dividing memory mat MT into a plurality of memory sub blocks MSB, only the memory sub block that includes a selected memory cell is driven so that current consumption is reduced. In addition, the number of memory cells connected to a bit line (the memory cell column) in the selected memory sub block is reduced so that proportionate reduction in bit line capacitance is achieved, thereby increasing a read voltage appearing on the bit line at the time of memory cell selection.
FIG. 54
is a diagram showing in further detail the arrangement of memory mat MT shown in FIG.
53
. In
FIG. 54
, two memory sub blocks MSBa and MSBb included in memory mat MT are shown. Local I/O line pairs LIOa to LIOd are provided which are shared by two memory sub blocks MSBa and MSBb aligned in the row direction. Local I/O line pairs LIOa to LIOd extend along memory sub blocks MSBa and MSBb in the column direction, and another local I/O line pair is provided for an adjacent memory sub block, which is not shown in the drawing.
Word line shunt region WS is provided between memory sub blocks MSBa and MSBb, in which main I/O line pairs MIOa to MIOd are arranged. These main I/O line pairs MIOa to MIOd are shared by memory sub blocks aligned in the column direction. The local I/O line pairs provided for the memory sub block selected by the row decoder, not shown, are connected to the main I/O line pairs.
A column selection signal from a column decoding circuit CDK included in column decoder CD is transmitted onto column selection line CSL arranged over the memory sub blocks in the column direction. Column selection line CSL is shared by the memory sub blocks aligned in the column direction, for transmitting the column selection signal to the memory sub blocks. Main amplifiers MAPa to MAPd are respectively provided for main I/O line pairs MIOa to MIOd, for performing amplification of data on the main I/O line pairs when activated.
In the arrangement shown in
FIG. 54
, when column selection line CSL is selected, the memory cells corresponding to four columns are selected in memory sub block MSBb. Thereafter, the columns are respectively connected to local I/O lines LIOa to LIOd, and then to main I/O line pairs MIOa to MIOd.
Eight such arrangements shown in
FIG. 54
are provided in the row direction. In the case of a four way method where four sense amplifiers (columns) are selected by a single column selection line CSL and connected to the local I/O line pairs, eight memory sub blocks are connected to the main I/O line pairs through the local I/O line pairs in sixteen memory sub blocks, and 4·8=32-bit data can be simultaneously selected in total. In this case, 2K(=128·16) sense amplifiers are provided in the row direction and memory cell data is latched at each sense amplifier. Therefore, 32-bit data designated by a column address is selected out of 2-Kbit data.
As shown in
FIG. 52
, four memory mats MT are provided in the semiconductor memory device, so that 128-bit word data can be transferred in a chip. When the mat is used as a bank, data of 32-bit word per bank is input/output.
FIG. 55
is a diagram schematically showing an arrangement of a mat of a conventional 256-M bit DRAM. Referring to
FIG. 55
, the DRAM includes memory mats MT
0
to MT
7
aligned in the row direction and memory mats MT
8
to MT
15
arranged facing to memory mats MT
0
to MT
7
. Peripheral circuitry PH is provided in the row direction between memory mats MT
0
to MT
7
and MT
8
to MT
15
. Peripheral circuitry PH includes a data input/output circuit and an address signal and external control signal input circuit.
Each of memory mats MT
0
to MT
15
has 16-M bit storage capacity. Main word driver groups MWD are arranged between the adjacent memory mats. In the 256-M bit DRAM, in order to drive word lines into a selected state at high speed, a hierarchical structure of main and sub word lines is employed. A memory cell is connected to the sub word line, but not to the main word line. A sub word line driver is arranged between the main and sub word lines. The main word line of small load capacitance is driven into the selected state at high speed and, responsibly, the sub word line provided at the remote end thereof is also driven into the selection state at high speed.
Each of memory mats MT
0
to MT
15
shown in
FIG. 55
is divided into a plurality of memory sub blocks MSB in the row and column directions as in the case of the above mentioned memory mats shown
FIGS. 53 and 54
. The memory sub block is increased in size with the provision of the sub word line drive circuit, so that it has 128-Kbit (512 rows·256 columns) storage capacity, or a double storage capacity of the arrangement shown in
FIGS. 53 and 54
. Thus, memory mat MT (MT
0
to MT
15
) is divided into eight memory sub blocks in the row direction. The arrangements of the local I/O line pairs and global I/O line pairs are the same as those shown in FIG.
54
. Accordingly, 4·4=16-bit memory cells are selected in a single mat for data input/output. When the DRAM shown in
FIG. 55
has a four-bank structure, data of 64-bit word per bank can be input/output as a single bank is formed of four memory mats.
In the conventional semiconductor memory device (DRAM), da

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