Fast accessible dynamic type semiconductor memory device

Details Fast accessible dynamic type semiconductor memory device Fast accessible dynamic type semiconductor memory device

1999-05-21

2001-01-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050

Reexamination Certificate

active

06175532

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a dynamic type semiconductor memory device which is accessible at a high speed.
2. Description of the Background Art
FIG. 97
schematically illustrates the structure of a main part of a conventional semiconductor memory device. Referring to
FIG. 97
, the semiconductor memory device includes a plurality of array blocks MBa to MBn. Each of the array blocks MBa includes a plurality of memory cells MC arranged in a form of rows and columns, a plurality of word lines WL arranged in correspondence to the respective rows and connected with the memory cells of the corresponding rows, and a plurality of bit line pairs BLP arranged in correspondence to the respective columns and connected with the memory cells of the corresponding columns.
FIG. 97
representatively illustrates a single word line WL and a single bit line pair BLP in each of the array blocks MBa to MBn.
X decoders XDa to XDn, sense amplifier bands SABa to SABn and selector bands STRa to STRn are arranged in correspondence to the array blocks MBa to MBn respectively, while a Y decoder YD and a global I/O bus GI/O are provided in common for the array blocks MBa to MBn.
The X decoders XDa to XDn decode supplied row address signals (paths therefor are not shown in
FIG. 97
) upon activation thereof, to drive word lines which are arranged in correspondence to addressed rows of the corresponding array blocks MBa to MBn respectively.
The sense amplifier bands SABa to SABn include sense amplifiers which are arranged in correspondence to the respective columns (the bit line pairs BLP) of the corresponding array blocks MBa to MBn respectively, and detect, amplify and latch memory cell data appearing on the corresponding bit line pairs BLP upon activation thereof.
The Y decoder YD decodes supplied column address signals, and transmits a column selection signal for selecting an addressed column onto a column selection line CS. The selector bands STRa to STRn connect the addressed column (the bit line pairs BLP) which is designated by an array block selection signal (not shown) to the global I/O bus GI/O in response to the column selection signal transmitted from the Y decoder YD onto the column selection signal line CS and to the array block selection signal.
The global I/O bus GI/O is provided with a read driver RDR which is activated in data reading for amplifying data on the global I/O bus GI/O for transmission onto an internal read/write bus RWBS, and a write driver WDR which is activated in data writing for buffering data on the internal read/write bus RWBS for transmission to the global I/O bus GI/O.
An output buffer OBF which is activated in data reading for buffering the data on the internal read/write bus RWBS for outputting to a data input/output terminal DQ, and an input buffer IBF which is activated in data writing for forming internal write data from a data signal received from the data input/output terminal DQ for transmission to the internal read/write bus RWBS are provided between the read/write bus RWBS and the data input/output terminal DQ.
In the semiconductor memory device shown in
FIG. 97
, only one of the plurality of array blocks MBa to MBn is activated. In a state referred to as “array activation”, a word line is selected in an array so that data of a memory cell which is connected with the selected word line is read onto each bit line pair BLP and amplified by an associated sense amplifier. Data is written in/read from only an array block which is designated by an array block selection signal.
FIG. 98
illustrates the internal structure of each of the array blocks MBa to MBn shown in
FIG. 97
in detail. This
FIG. 98
representatively shows only the structure of a portion which is related to one column of a single array block, with only a single word line WL shown.
Referring to
FIG. 98
, the bit line pair BLP includes bit lines BL and ZBL transmitting data signals which are complementary to each other. A memory cell MC which is arranged at the crossing between the bit line BL and the word line WL includes a capacitor MQ storing data in the form of electric charges, and an access transistor MT formed by an n-channel MOS transistor and connecting the memory capacitor MQ to the bit line BL in response to a signal potential on the word line WL.
A sense amplifier SA included in the sense amplifier band SAB includes a p-channel MOS transistor P
1
having a first conduction terminal connected with the bit line BL, a control gate connected with the bit line ZBL, and a second conduction terminal coupled to receive a sense amplifier activation signal Vp, a p-channel MOS transistor P
2
having a first conduction terminal connected with the bit line ZBL, a control gate connected with the bit line BL, and a second conduction terminal coupled to receive the sense amplifier activation signal Vp, an n-channel MOS transistor N
4
having a first conduction terminal connected with the bit line BL, a control gate connected with the bit line ZBL, and a second conduction terminal coupled to receive a sense amplifier activation signal Vn, and an n-channel MOS transistor N
5
having a first conduction terminal connected with the bit line ZBL, a control gate connected with the bit line BL, and a second conduction terminal coupled to receive the sense amplifier activation signal Vn.
The p-channel MOS transistors Pl and P
2
form a flip-flop, to drive one having a higher potential of the bit lines BL and ZBL to a high level upon activation (high level) of the sense amplifier signal Vp. The n-channel MOS transistors N
4
and N
5
also form a flip-flop, to drive one having a lower potential of the bit lines BL and ZBL to a low level upon activation (low level) of the sense amplifier activation signal Vn.
A local I/O bus LI/OA consisting of local I/O lines LIOa and LIOb is arranged for an array block MB#A (any of MBa to MBn).
The selector band STR includes a column selection gate CSEL provided for the bit lines BL and ZBL to connect these bit lines BL and ZBL to the local I/O lines LIOa and LIOb in response to a column selection signal CS (a signal which is transmitted onto the column selection signal line shown in FIG.
97
and denoted by the same symbol), and a block selection gate BSELA for connecting the local I/O lines LIOa and LIOb respectively to global I/O lines GIOa and GIOb forming the global I/O bus GI/O in response to an array block selection signal TGA. The column selection gate CSEL includes a transfer gate N
6
formed by an n-channel MOS transistor arranged between the bit line BL and the local I/O line LIOa, and a transfer gate N
7
formed by an n-channel MOS transistor arranged between the bit line ZBL and the local I/O line LIOb. The block selection gate BSELA includes a transfer gate N
8
formed by an n-channel transistor arranged between the local I/O line LIOa and the global I/O line GIOa, and a transfer gate N
9
formed by an n-channel MOS transistor arranged between the local I/O line LIOb and the global I/O line GIOb.
FIG. 98
also shows a block selection gate BSELB which is provided for another array block MB#B. This block selection gate BSELB connects a local I/O line arranged for this array block MB#B to the global I/O bus GI/O in response to a block selection signal TGB.
The read driver RDR differentially amplifies complementary signals appearing on the global I/O bus GI/O, for transmission to the internal read/write bus RWBS. The write bus driver WDR amplifies the signals on the internal read/write bus RWBS, forms complementary write data, and transmits the amplified onto the global I/O lines GIOa and GIOb.
The bit lines BL and ZBL are provided with an equalize/precharge circuit EP which in turn precharges and equalizes the bit lines BL and ZBL at a prescribed precharge potential Vpr in response to an equalization signal EQ. This equalize/precharge circuit EP includes an n-channel MOS transistor Ni for connecting the bit lines BL and ZBL wi

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