Fast access circuit for dynamic type semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

365210, 365226, 307279, G11C 800, G11C 702, H03K 338

Patent

active

048336564

ABSTRACT:
A semiconductor memory device comprises a row address buffer (5') which operates in response to an external address signal (A.sub.0 .about.A.sub.7) for generating an internal address signal (A.sub.n, A.sub.n) from the supplied external address signal. Row decoding is performed in response to an external clock signal RAS.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4651029 (1987-03-01), Oritani
patent: 4675850 (1987-06-01), Kumanoya et al.

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