Patent
1975-03-14
1978-03-28
Brown, Thomas W.
H04J 300
Patent
active
040816109
ABSTRACT:
The disclosure describes a control memory for addressing inlet and outlet switching stages of a three stage digital switch. The control memory comprises two identical random access memories (RAM's) each having an address storage capacity equal to half the number of simplex connections which can be made through either stage of the switch. The arrangement described allows a large saving in the number of memory bits necessary to address the inlet and outlet switching stages and enables fast access of the control memory for the purpose of establishing or terminating connections.
REFERENCES:
patent: 3761894 (1973-09-01), Pilc et al.
patent: 3851105 (1974-11-01), Regnier et al.
patent: 3867579 (1975-02-01), Colton et al.
patent: 3878338 (1975-04-01), Hardy
patent: 3894189 (1975-07-01), Edstrom et al.
patent: 3920914 (1975-11-01), Regnier et al.
patent: 3927267 (1975-12-01), Voyer et al.
Stipcevic Franko
Valastro Bartolo
Brown Thomas W.
L.M. Ericsson Pty. Ltd.
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