Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-05-10
2003-09-23
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C324S322000
Reexamination Certificate
active
06624777
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Japanese Application No. 2001-141186 filed May 11, 2001.
BACKGROUND OF THE INVENTION
The present invention relates to a fast A/D (Analog to Digital) conversion signal processor, an RF (Radio Frequency) receiver circuit, a digital receiver front end circuit, an MRI (Magnetic Resonance Imaging) apparatus, and a fast A/D conversion device. More particularly, the invention relates to a fast A/D conversion signal processor which, even in the presence of discordance in terms of timing between the output of digital data from a fast A/D converter and the clock signal for a digital signal process used by a digital signal process section, can absorb the discordance and deliver the digital data from the fast A/D converter to the digital signal process section properly, an RF receiver circuit and digital receiver front end circuit which can be used for the fast A/D conversion signal processor, an MRI apparatus which uses the fast A/D conversion signal processor, and a fast A/D conversion device which can be used for the fast A/D conversion signal processor.
In recent years, digitization of signal processing is advancing also in MRI apparatus. Specifically, in an advanced scheme, an NMR signal received by a receiving coil is converted with a fast A/D converter into digital data, with resulting digital-data being delivered to a digital signal process section, which implements a digital signal processing (e.g., digital filtering) for the digital data, with resulting data being delivered to a computer, which implements an image recomposing process or the like.
In delivering digital data released by a fast A/D converter to a digital signal process section, there emerges the discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for a digital signal process used by the digital signal process section.
This timing discordance is the natural consequence in case the clock signal for the fast A/D converter and the clock signal for the digital signal process are produced independently of each other, and it also emerges when one clock signal is used distributively as both clock signals. Conceivable causes are that the clock signal circuit for the fast A/D converter uses an RF pulse transformer for generating differential RF clock signals which are needed by the fast A/D converter, and that there is the disparity in the timing of output of digital data from the fast A/D converter among circuit devices, and that there is a difference between the delay time of a digital data transfer system and the delay time of a clock signal transfer system.
Hence, in the presence of the above-mentioned discordance of timing, it is problematic in that the fast A/D converter can possibly fail to deliver digital data to the digital signal process section properly.
SUMMARY OF THE INVENTION
Therefore, a first object of the present invention is to provide a fast A/D conversion signal processor which, even in the presence of discordance in terms of timing between the output of digital data from a fast A/D converter and the clock signal for a digital signal process used by a digital signal process section, can absorb the discordance and deliver the digital data from the fast A/D converter to the digital signal process section properly.
A second object of the present invention is to provide an RF receiver circuit and digital receiver front end circuit which can be used for the fast A/D conversion signal processor.
A third object of the present invention is to provide an MRI apparatus which uses the fast A/D conversion signal processor.
A fourth object of the present invention is to provide a fast A/D conversion device which can be used for the fast A/D conversion signal processor.
At a first viewpoint, the present invention resides in a fast A/D conversion signal processor which is characterized by comprising a fast A/D converter which converts an input analog signal into digital data at an operation speed of 20 MHz or higher, a digital signal process section which implements a digital signal processing for the digital data, and data memory means which stores the digital data released by the fast A/D converter in synchronism with a data ready signal provided by the fast A/D converter and reads out the stored digital data and delivers to the digital signal process section in synchronism with a clock signal for a digital signal process used by the digital signal process section.
In the fast A/D conversion signal processor of the first viewpoint, digital data is stored in the data memory means at the timing of output of the digital data from the fast A/D converter (at the timing which is based on the data ready signal). Digital data is read out of the data memory means and delivered to the digital signal process section at the operation timing of the digital signal process section (at the timing which is based on the clock signal for the digital signal process). In consequence, even in the presence of discordance in terms of timing between the output of digital data from the fast A/D converter and the clock signal for the digital signal process used by the digital signal process section, the discordance is absorbed by the intervention of the data memory means and the digital data can be delivered from the fast A/D converter to the digital signal process section properly.
In the above-mentioned arrangement, the “data ready signal” signifies a “signal indicative of the output period of valid data”, and it may be called “data valid signal”.
At a second viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized in that the data memory means includes a dual-clock-synchronous FIFO (First-In-First-Out), a write control circuit which responds to a start signal indicative of the commencement of storing to store the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO in synchronism with the data ready signal, and a readout control circuit which responds to an empty signal provided by the dual-clock-synchronous FIFO to read the digital data out of the dual-clock-synchronous FIFO in synchronism with the clock signal for the digital signal process.
In the fast A/D conversion signal processor of the second viewpoint, it is possible to write the digital data released by the fast A/D converter into the dual-clock-synchronous FIFO based on the input of the start signal from the outside. Digital data is read out of the dual-clock-synchronous FIFO in response to the empty signal which is produced when the digital data is written into the dual-clock-synchronous FIFO, and consequently the digital data can be delivered from the fast A/D converter to the digital signal process section properly.
At a third viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized in that the readout control circuit produces and releases a sync ready signal for indicating to the outside that digital data is amid the readout of the dual-clock-synchronous FIFO.
In the fast A/D conversion signal processor of the third viewpoint, it is possible to know the output timing of digital data from the dual-clock-synchronous FIFO by monitoring the sync ready signal.
At a fourth viewpoint, the present invention resides in the fast A/D conversion signal processor of the foregoing arrangement, which is characterized by comprising a high-stability crystal oscillator, an RF multiplying circuit which produces an RF clock signal having a frequency that is a multiple of the frequency of the output signal of the high-stability crystal oscillator, and an RF pulse transformer which produces differential RF clock signals to be used by the fast A/D converter from the RF clock signal.
With the fast A/D conversion signal processor of the fourth viewpoint, it is possible to produce properly the differential RF clock signals needed by the fast A/D converter.
At a fifth view
GE Medical Systems Global Technology Company LLC
Horton Esq. Carl B.
Wamsley Patrick
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