Fast 2-input 32-bit domino adder

Details Fast 2-input 32-bit domino adder Fast 2-input 32-bit domino adder

1997-05-05

2001-03-20

Lee, Thomas C. (Department: 2182)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S711000, C708S712000

Reexamination Certificate

active

06205463

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of digital (binary) adders, particularly those employing carry look-ahead.
2. Description of Related Art
Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, the carry bit that results from the addition of lesser significant bits must be considered. This can easily be done by rippling a carry signal through the entire addition chain as the addition is performed. A problem with this, particularly for relatively large words (e.g., 32 bits) is that substantial time is required to ripple the carry signal. Since adders are often performing logic functions in critical time paths, the time needed to ripple the carry signal can slow up the microprocessor. This problem is dealt with in the prior art with carry look-ahead circuits, skip-carry circuits and with different partitioning of group circuitry. These circuits are discussed in U.S. Pat. No. 4,737,926.
Thus, what is needed is an improved adder that has fewer delays along critical paths in the adder and provides substantial improvement in terms of speed of operation when compared to prior art adders.
SUMMARY OF THE INVENTION
In one embodiment, an adder comprises a first block, a second block, and a third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.


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