Fast 16 bit, split transaction I/O bus

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

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Details

370503, H04J 306

Patent

active

060883707

ABSTRACT:
A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.

REFERENCES:
patent: 4719621 (1988-01-01), May
patent: 5101347 (1992-03-01), Balakrishnan
patent: 5193090 (1993-03-01), Filipiak et al.
patent: 5325492 (1994-06-01), Bonevento et al.
patent: 5361252 (1994-11-01), Sallberg et al.
patent: 5404171 (1995-04-01), Golstein et al.
patent: 5448708 (1995-09-01), Ward
patent: 5467464 (1995-11-01), Oprescu
patent: 5491799 (1996-02-01), Kreuzenztein et al.
patent: 5499338 (1996-03-01), Gercekci
patent: 5548733 (1996-08-01), Sarangdhar
patent: 5574862 (1996-11-01), Marianetti, II
patent: 5625779 (1997-04-01), Solomon
patent: 5657457 (1997-08-01), Gaskins
patent: 5659718 (1997-08-01), Osman
patent: 5668971 (1997-09-01), Neufeld
patent: 5671441 (1997-09-01), Glassen et al.
patent: 5729760 (1998-03-01), Poisner
patent: 5751969 (1998-05-01), Kapoor
patent: 5758166 (1998-05-01), Ajonovic
patent: 5768545 (1998-06-01), Solomon
patent: 5768546 (1998-06-01), Kwon
patent: 5771356 (1998-06-01), Leger et al.
patent: 5784579 (1998-07-01), Pawlowski
Galles, Willaims, "Performance Optimizations, Implementation, and Cerification of SGI Challenge Multiprocessor", Silicon Graphics Computer Systems, Proceedings of the Twenty-Seventh Annual Hawaii International Conference on System Sciences, 1994.

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