Fanned out interconnect via structure for electronic package...

Details Fanned out interconnect via structure for electronic package... Fanned out interconnect via structure for electronic package...

2002-05-14

2004-11-02

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000, C257S776000

Reexamination Certificate

active

06812576

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic device packaging. More particularly, the present invention relates to the design of an interconnect via structure for an electronic package substrate.
BACKGROUND OF THE INVENTION
An electronic package substrate includes an interconnect structure for routing signals from conductive traces or pads on the top surface of the substrate to conductive traces, pads, or solder balls on the bottom surface of the substrate. For example, electronic chips are often mounted in ball grid array (“BGA”) packages that can be easily attached to a printed circuit board (“PCB”) or an electronic component. A typical BGA package includes an electronic chip that is physically and electronically connected to a BGA substrate, which includes an interconnect arrangement that provides conductive paths between points on the chip-mounting substrate surface and corresponding solder balls located on the board-mounting substrate surface. BGA packages are often utilized for high speed electronic devices, e.g., circuits that handle input and/or output signals having data rates of up to 40 Gbps. The trace-to-via and via-to-pad transitions represent electrical discontinuities that limit the bandwidth of a signal propagating through the package. Indeed, in high speed applications, these transitions can cause problematic impedance mismatching, high insertion loss, and high reflection loss.
For very high data rate applications such as OC-768 (40 Gbps), trace-to-via and via-to-pad transitions can be avoided by using connectorized packages. Such packages employ connectors that receive the high speed signals directly from the top surface of the package substrate. Such connectorized packages can be very complex and expensive to manufacture. In addition, the package substrate must be unnecessarily thick to accommodate the high speed connectors, which can degrade the signal integrity of other signals handled by the interconnect structure of the electronic package.
In certain narrowband applications, the package substrate may employ a layout-based filter as a solution to the problems introduced by the via transitions. This approach can be risky because the center frequency of the filter may vary in response to manufacturing tolerances, thus rendering some of the packages unusable. Furthermore, this approach cannot be used for broadband applications.
BRIEF SUMMARY OF THE INVENTION
An electronic package substrate according to the present invention includes an interconnect structure comprising fanned out vias. The design of the vias results in very low return and insertion losses over a broadband frequency range, which makes the package suitable for high speed applications such as SONET OC-768. The interconnect via structure need not employ bulky high speed connectors that can adversely affect other signals within the package substrate.
The above and other aspects of the present invention may be carried out in one form by an electronic device interconnect substrate comprising a signal source layer, a terminal pad layer, and a plurality of interconnect vias, each extending between the signal source layer and the terminal pad layer, the plurality of vias corresponding to one lateral pitch at the signal source layer and another lateral pitch at the terminal pad layer.


REFERENCES:
patent: 5831330 (1998-11-01), Chang
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6329610 (2001-12-01), Takubo et al.

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