Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-10-31
2004-07-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S461000, C438S462000, C438S113000, C438S117000, C438S617000
Reexamination Certificate
active
06759311
ABSTRACT:
FIELD OF THE INVENTION
In general, the invention relates to processing of semiconductor wafers and has particular applicability to formation of interconnect elements on semiconductor devices while in wafer form.
BACKGROUND OF THE INVENTION
As is known, microelectronic or integrated circuits are manufactured by forming identical such circuits on each of a many devices or dice on a semiconductor wafer. Eventually, the wafer is divided or “singulated” into the individual devices or dice. Typically, this involves cutting, e.g., using a very fine saw, laser, kerfing tool, dicing tool, or the like, the wafer along spaces between the dice, which spaces customarily are referred to as “scribe streets” or “kerf lines.”
Each of the individual die on a wafer include terminals that function as connection points into and out of the microelectronic circuit on the die. Eventually, interconnect elements are attached to the terminals. In use, these interconnect elements form electrical connections with an external element, allowing the external element and the die to communicate electrically. Examples of such external elements include without limitation printed circuit boards, other die, and other electronic elements.
Commonly used interconnect elements include metal pins, solder balls, metal bumps, and metal pads. Resilient, elongated, spring-type interconnect elements, which have recently been developed, may also be used. Examples of such interconnect elements are described in this application and in applications incorporated herein by reference.
Many, but not all, semiconductor devices (i.e., die) are also packaged. That is, a protective material is formed on or around at least a portion of the die. The protective material may serve a number of functions, including without limitation protecting the die, strengthening the die, and dissipating heat generated by the die. Plastics, metals, ceramics, resins, and organic materials are nonexclusive examples of commonly used packaging materials. Of course, the interconnect elements attached to a die's terminals must extend through the die's packaging.
Traditionally, a wafer is singulated into individual die before interconnect elements are attached to the dice's terminals and before the dice are packaged. It is known, however, to attach interconnect elements to the terminals of a die and/or package the die while the die is still in wafer form (that is, before the wafer has been singulated). This is sometimes referred to as “wafer level packaging.”
According to conventional wisdom, the interconnect elements and the packaging materials formed on a die of an unsingulated wafer must be located entirely within the boundary of the die on the wafer. That is, neither the interconnect elements nor the packaging materials may extend beyond the boundary of the die into the scribe streets surrounding the die. This limitation arises primarily because such interconnect elements or packaging materials would interfere with any subsequent attempt to cut the wafer along its scribe streets.
That interconnect elements and packaging materials are confined to the area of the die imposes disadvantages on the use of wafer level packaging. One such disadvantage is a corresponding restriction on the pitch and layout of the interconnect elements. Simply put, the pitch of interconnect elements located entirely within the boundary of a die must be finer or tighter than the pitch of interconnect elements that fan out beyond the boundary of the die (as is the case where the interconnect elements are attached to the die after it has been singulated from the wafer). Of course, the finer the pitch of the interconnect elements on the die, the finer the pitch that is required of the connection receptacles on the external element (e.g., printed circuit board) to which the die will be connected in use. Generally speaking, the finer the pitch of the connection receptacles, the greater the cost of the external element.
Similarly, requiring that the interconnect elements be confined entirely within the boundary of the die also limits the pattern or layout of the interconnect elements. That is, the greater the area in which the interconnect elements can be located, the more freedom there is in locating each interconnect element and therefore the more freedom there is in selecting the pattern or layout of the interconnect elements. Again, the loss of such freedom associated with wafer level packaging increases costs.
As should be apparent, a way of packaging a die—and in particular, of attaching interconnect elements to terminals of the die—while in wafer form that allows the interconnect elements to fan out beyond the boundaries of the die is needed.
SUMMARY OF THE INVENTION
The present invention relates to processing of semiconductor devices while in wafer form and more particularly to formation of interconnect elements that fan out beyond the boundary of a die. An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.
REFERENCES:
patent: 3447235 (1969-06-01), Rosvold et al.
patent: 3550261 (1970-12-01), Schroeder
patent: 3849872 (1974-11-01), Hubacher
patent: 4032058 (1977-06-01), Riseman
patent: 4086375 (1978-04-01), LaChapelle et al.
patent: 4137867 (1979-02-01), Aigo
patent: 4281449 (1981-08-01), Ports et al.
patent: 4486945 (1984-12-01), Aigoo
patent: 4732313 (1988-03-01), Kobayashi et al.
patent: 4751199 (1988-06-01), Phy
patent: 5070297 (1991-12-01), Kwon et al.
patent: 5185502 (1993-02-01), Shepherd et al.
patent: 5195237 (1993-03-01), Cray et al.
patent: 5210939 (1993-05-01), Mallik et al.
patent: 5323035 (1994-06-01), Leedy
patent: 5391521 (1995-02-01), Kim
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5513430 (1996-05-01), Yanof et al.
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 5666190 (1997-09-01), Quate et al.
patent: 5677566 (1997-10-01), King et al.
patent: 5701666 (1997-12-01), DeHaven et al.
patent: 5723894 (1998-03-01), Ueno et al.
patent: 5764486 (1998-06-01), Pendse
patent: 5786270 (1998-07-01), Gorrell et al.
patent: 5820014 (1998-10-01), Dozier, II et al.
patent: 5824177 (1998-10-01), Yoshihara et al.
patent: 5828226 (1998-10-01), Higgins et al.
patent: 5829128 (1998-11-01), Eldridge et al.
patent: 5847445 (1998-12-01), Wark et al.
patent: 5897326 (1999-04-01), Eldridge et al.
patent: 6002266 (1999-12-01), Briggs et al.
patent: 6023103 (2000-02-01), Chang et al.
patent: 6031282 (2000-02-01), Jones et al.
patent: 6053395 (2000-04-01), Sasaki
patent: 6064213 (2000-05-01), Khandros et al.
patent: 6074896 (2000-06-01), Dando
patent: 6080596 (2000-06-01), Vindasius et al.
patent: 6117694 (2000-09-01), Smith et al.
patent: 6174744 (2001-01-01), Watanabe et al.
patent: 6184576 (2001-02-01), Jones et al.
patent: 6207477 (2001-03-01), Motooka et al.
patent: 6255126 (2001-07-01), Mathieu et al.
patent: 6336269 (2002-01-01), Eldridge et al.
patent: 6350664 (2002-02-01), Haji et al.
patent: 6365443 (2002-04-01), Hagiwara et al.
patent: 6406937 (2002-06-01), Hedler
patent: 147090 (1989-02-01), None
patent: 2034949 (1990-02-01), None
patent: 3142847 (1991-06-01), None
patent: 6018555 (1994-01-01), None
patent: 7333232 (1995-12-01), None
patent: 8306708 (1996-11-01), None
patent: WO 00/03569 (2000-01-01), None
patent: WO 00/33096 (2000-06-01), None
Goldstein, “Packages Go Vertical,” IEEE Spectrum, pp. 46-51 (Aug. 2001).
Bracken et al., “Assembly and Packaging,” Handbook of Semiconductor Manufacturing, pp. 999-1025 (New York 2000).
“Method of Testing Chips and Joining Chips to Substrates,” 2244 Research Disclosure, No. 322 (Emsworth, Great Britain Feb. 1991).
Eldridge Benjamin N.
Khandros Igor Y.
Burraston N. Kenneth
FormFactor Inc.
Merkadeau Stuart L.
Niebling John F.
Roman Angel
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