Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1987-06-10
1989-08-01
Zazworsky, John
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307448, 307450, 307475, 307542, 307558, 307574, 307581, 357 22, H03K 1716, H03K 19017, H01L 2980
Patent
active
048535613
ABSTRACT:
A new family of memory cells and digital-logic gates use an enhancement-mode driver, a voltage-level shifter, and a current regulator to provide improved noise margins and large logic swings. The voltage-level shifter and the current regulator are connected in series between an input and the control electrode of the driver. The voltage-level shifter establishes a voltage drop which is independent of current, while the current regulator establishes a constant current in the series path to the control electrode which is independent of voltage. The driver is an enhancement-mode device, such as a JFET, MESFET, or BJT.
REFERENCES:
patent: 2989713 (1961-06-01), Warner, Jr.
patent: 4110841 (1978-08-01), Schroeder
patent: 4149099 (1979-04-01), Nagami
patent: 4321492 (1987-03-01), Hollingsworth
patent: 4349894 (1982-09-01), Caudel
patent: 4375677 (1983-03-01), Schuermeyer
patent: 4400799 (1983-08-01), Gudger
patent: 4405870 (1983-09-01), Eden
patent: 4554644 (1985-11-01), Chen et al.
patent: 4578601 (1986-03-01), McAlister et al.
patent: 4607350 (1986-08-01), Scianna
patent: 4686396 (1987-08-01), Law et al.
M. M. Mano, Digital Logic and Computer Design, Prentice-Hall, p. 67 (1979).
Inst. Phys. Conf., No. 339, pp. 227-236 (1977).
IEEE, JSCS, SC-12, pp. 485-496 (1977).
IEEE, ED-29, pp. 1110-1115 (1982).
IEEE, EDL-7, p. 145 (Mar. 1986).
IEEE, JSCC, SC-19, pp. 10-22 (1984).
S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., Wiley Interscience, p. 618 (1981).
R. M. Warner, Jr., "A New Passive Semiconductor Component", IRE National Convention Record, vol. 6, p. 43, 1958.
Motorola Inc., "I/C Logic for Control Functions in High-Noise Industrial Environments" MC660 Series, Mar. 1971 (4 pages).
J. Lohstroh, the Punch-Through Device as a Passive Exponential Load in Fast Static Bipolar RAM Cells, IEEE, JSSX, SC-14, pp. 840-844 (1979).
J. Lohstroh, Worst-Case Static Noise Margin Criteria for Logic Circuits and their Mathetical Equivalence, IEEE, JSSC, SC-18, pp. 803-806 (1983).
R. J. Gravrok and R. M. Warner, Jr., Logic Family and Memory-Cell Designs Providing Abrupt Voltage Transitions and High Noise Margins.
Electronics, Sep. 3, 1987, p. 45, beginning in the middle of the second column entitled "Noise Margins".
Regents of the University of Minnesota
Wanbach Margaret Rose
Zazworsky John
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