False lock detection circuit and false lock detection...

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

Reexamination Certificate

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Details

C375S376000

Reexamination Certificate

active

11108741

ABSTRACT:
Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data signal on a basis of the clock signal, and detecting a data pattern in which adjacent pieces of data at at least three consecutive bits differ from each other; a phase period shift detector detecting a shift between periods of phases at a change point of the data signal and a change point of the clock signal; and a determining section determining whether a false lock has occurred on a basis of results of detection of the pattern detector and the phase period shift detector.

REFERENCES:
patent: 5123030 (1992-06-01), Kazawa et al.
patent: 5255292 (1993-10-01), LaRosa et al.
patent: 6807225 (2004-10-01), Tonietto et al.
patent: 04-132048 (1992-05-01), None

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