Pulse or digital communications – Synchronizers
Reexamination Certificate
2011-05-03
2011-05-03
Corrielus, Jean B (Department: 2611)
Pulse or digital communications
Synchronizers
C331SDIG002, C327S141000, C327S160000
Reexamination Certificate
active
07936853
ABSTRACT:
A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
REFERENCES:
patent: 6331792 (2001-12-01), Tonietto
patent: 6853696 (2005-02-01), Moser et al.
patent: 7424082 (2008-09-01), Choi
patent: 7668271 (2010-02-01), Kim et al.
patent: 2004/0001483 (2004-01-01), Schmidt et al.
Do Viet Linh
Eker Mehmet Mustafa
Pang Simon
Applied Micro Circuits Corporation
Corrielus Jean B
Law Office of Gerald Maliszewski
Maliszewski Gerald
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