Failure information processing in automatic memory tester

Details Failure information processing in automatic memory tester Failure information processing in automatic memory tester

1987-06-08

1989-10-24

Smith, Jerry

Excavating

371 24, 371 27, 371 291, G01R 3128, G06F 1100

Patent

active

048766852

ABSTRACT:
Automatic memory tester apparatus for processing failure information of a memory under test (MUT) including a high speed pattern generator for providing digital test patterns to the MUT for storage of data at MUT addresses in the MUT, a failure processor for comparing outputs from the MUT with expected outputs to obtain failure information, and a fail map random access memory (RAM) having fail map addresses corresponding to the MUT addresses and connected to receive the failure information and store it at corresponding fail map addresses. The fail map addresses includes bits to address individual bits of multibit words. An address generator of the high speed pattern generator for randomly addresses and reads individual bits of the multibit words to provide a serial bit output for display. Relative positions of the display related to topical positions of associated memory elements on the MUT.

REFERENCES:
patent: 4450560 (1984-05-01), Conner
patent: 4451918 (1984-05-01), Gillette
patent: 4736373 (1988-04-01), Schmidt
Kurth, R., et al., "Universal Physical Memory Bit Fail Map", IBM Technical Bulletin, vol. 26, No. 11, Apr. 1984, pp. 5996-6000.

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