Failure detection system for a mirrored memory dual controller d

Details Failure detection system for a mirrored memory dual controller d Failure detection system for a mirrored memory dual controller d

1996-05-30

1997-12-16

Nguyen, Hoa T.

39518318, 39518204, 39518207, G06F 1100

Patent

active

056995105

ABSTRACT:
In a disk storage system having dual controllers and mirrored memory therebetween, arbitration logic associated with each controller generates state transition signals to identify the mirrored memory access status for the controller generating the signal. Each arbitration logic also monitors the state transition signals of the other. A failure in the mirrored memory system between the dual controllers is detected by one controller sensing an incorrect state transition signal communicated from the other controller. A failure is also detected by one controller not sensing a state transition signal from the other within a specified timeout period. Memory refresh cycles are tapped to cause the arbitration logic to cycle through state transition signals thereby forcing each controller to attempt a mirrored memory access on a regular basis whereby a memory system failure may be detected.

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