Failure analysis system of semiconductor memory device

Details Failure analysis system of semiconductor memory device Failure analysis system of semiconductor memory device

2005-03-22

2005-03-22

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

C716S030000, C702S185000

Reexamination Certificate

active

06871168

ABSTRACT:
In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.

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