Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2001-07-19
2004-01-13
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S058000, C702S081000, C702S180000, C714S738000
Reexamination Certificate
active
06678623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure analysis device and a failure analysis method, and particularly to an automatic failure analysis device and an automatic failure analysis method for examining chips having logic LSIs fabricated therein or chips having system LSIs having logic regions fabricated therein. The present invention relates also to a semiconductor device manufacturing method using the failure analysis method.
2. Description of the Background Art
In the failure analysis of semiconductor devices such as LSIs, light emission analysis is one of the most common analysis methods. In the light emission analysis, a light detecting device which can detect very weak photon-level light is used to detect very weak light emitted at leakage locations so as to determine the failure locations. This technique can be applied not only to analysis of leakage failures such as power-supply leakage, standby leakage, etc. but also to analysis of operation failures accompanied by leakage. The light emission analysis is indispensable analysis means particularly in identifying failure locations in logic LSIs or in logic regions of system LSIs in which electrical testing cannot successfully identify failure locations.
A conventional light emission analysis for examining logic LSIs is now described.
FIG. 20
is a block diagram showing the structure of a conventional failure analysis device. The wafer
101
has a matrix of a plurality of chips to be tested (not shown). Each chip has a logic LSI fabricated therein. The wafer
101
is placed on a wafer stage
102
.
A known probe card
105
is disposed to face toward the wafer surface of the wafer
101
. The probe card
105
has a plurality of probes
106
for making contact with electrode pads formed on the chips. A light detecting device
107
is disposed near the wafer surface of the wafer
101
. The light detecting device
107
is connected to a failure location analysis unit
108
. The conventional failure analysis device also has a recording unit
103
connected to the probe card
105
and a main control unit
104
connected to the probe card
105
and the wafer stage
102
.
FIG. 21
is a flowchart showing the procedure of light emission analysis using the conventional failure analysis device shown in FIG.
20
. First, in the step SP
7
A, an operator enters measurement conditions into the failure analysis device. More specifically, the operator enters data D
101
about conditions to be individually set into the main control unit
104
, so as to specify a plurality of wafers to be tested among a plurality of wafers stored in a wafer cassette, to specify a plurality of chips to be tested among a plurality of chips formed on each wafer, to specify test conditions about the test pattern, voltage application, etc.
Next, in the step SP
7
B, the first wafer
101
, or a wafer to be tested first among the plurality of wafers to be tested, is placed on the wafer stage
102
. Next, in the step SP
7
C, the wafer stage
102
moves the wafer
101
on the basis of a control signal S
101
provided from the main control unit
104
to align the first chip, or a chip to be tested first among the plurality of chips to be tested on the wafer
101
, with the light detecting device
107
. The probes
106
of the probe card
105
are then set into contact with given electrode pads formed on the chip.
Next, in the step SP
7
D, the probe card
105
applies a test pattern composed of a plurality of test vectors TB
1
to TBn to the chip on the basis of a control signal S
102
provided from the main control unit
104
. Next, in the step SP
7
E, the probe card
105
sequentially detects quiescent power supply currents (Iddq) which flow when the individual test vectors TB
1
to TBn are applied. The recording unit
103
then records the Iddq values I
1
to In sequentially provided from the probe card
105
.
Next, in the step SP
7
F, the operator refers to the Iddq values I
1
to In recorded in the recording unit
103
to identify an abnormality occurrence vector.
FIG. 22
is a diagram used to explain a method in which the operator identifies the abnormality occurrence vector. In the diagram, the horizontal axis shows the test vectors TB
1
to TBn and the vertical axis shows the current value. The test vectors are sequentially applied upon each input of a clock and the logic state changes. A large switching current flows at the instant the logic state changes and then the current value settles in quiescent state. The power-supply current which flows in this quiescent state is the quiescent power supply current (Iddq). The waveform shown in
FIG. 22
is recorded in the recording unit
103
and the operator refers to this waveform and specifies a test vector with which the Iddq value shows an abnormal value as the abnormality occurrence vector (the test vector TB
3
in the example shown in FIG.
22
).
Next, in the step SP
7
G, the operator enters data D
102
about the specified abnormality occurrence vector into the main control unit
104
. The probe card
105
then applies again the test pattern from the first test vector TB
1
to the abnormality occurrence vector to the chip on the basis of a control signal S
103
provided from the main control unit
104
and holds the state in which the abnormality occurrence vector is applied to the chip.
Next, in the step SP
7
H, the failure location on the chip is located through the light emission analysis. More specifically, with the abnormality occurrence vector applied to the chip, the light detecting device
107
detects light emission from the chip. The failure location analysis unit
108
then locates the failure location on the chip on the basis of data T about the location of the light emission provided from the light detecting device
107
.
Next, in the step SP
7
I, the main control unit
104
checks whether the chip currently in alignment is the last chip. When the step SP
7
I provides a decision “NO,” the flow moves to the step SP
7
J, where the next chip is aligned. The operations in and after the step SP
7
D are then applied to the aligned chip.
When the decision of the step SP
7
I is “YES,” the flow goes to the step SP
7
K, where the main control unit
104
checks whether the wafer
101
currently placed on the wafer stage
102
is the last wafer. When the step SP
7
K shows “NO,” the flow moves to the step SP
7
L, where the next wafer is placed on the wafer stage
102
. The operations in and after the step SP
7
C are then applied to that wafer.
When the decision made in the step SP
7
K is “YES,” the test is ended.
As explained above, the light emission analysis of logic LSIs requires that the light emission analysis be executed with the abnormality occurrence vector applied to the chip. However, with the conventional failure analysis device, the operator must refer to the current waveform recorded in the recording unit
103
to specify the abnormality occurrence vector.
Devices for automatically applying the light emission analysis to all or part of chips formed on a wafer include those disclosed in Japanese Patent Application Laid-Open Nos. 10-4128 (1998) and 10-223707 (1998), some of which are used in practice. However, these devices are designed to apply automatic light emission analysis to a plurality of chips under predetermined fixed conditions. Therefore these devices cannot be directly applied to the light emission analysis of logic LSIs in which the measurement conditions must be varied chip by chip because different abnormality occurrence vectors are specified among different chips.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a failure analysis device comprises: a test pattern applying portion for applying a test pattern composed of a plurality of test vectors to a test target; an abnormality occurrence vector specifying portion for specifying an abnormality occurrence vector which can activate a failure present in the test target from among the test pattern on the basis of detected values of quiescent power supply
Barlow John
Cherry Stephen J.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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