Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-04-04
2004-01-27
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S699000
Reexamination Certificate
active
06683604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a system adapted to visually display digital image data and, more particularly, to a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor.
2. Description of the Prior Art
Digital image data is input to a system adapted to visually display digital image data on a display device. Digital image data is input to a frame locked system one frame at a time at an input frame rate. A frame is an image displayed for viewing on a display device or panel at one time, i.e., one frame of data fits on the display device screen or panel. Each frame includes a rectangular array of pixels. Each pixel has one or more values, for example, a gray scale value for a monochrome display or red, green, and blue (RGB) values for a color display. The resolution of the array, i.e., the number of horizontal and vertical pixels, is often referred to as an image frame resolution. Common display frame resolutions include that shown in Table 1 indicating, in the second and third columns, the number of pixels in the vertical and horizontal dimensions, respectively:
TABLE 1
VGA
640
480
SVGA
800
600
XGA
1024
768
SXGA
1280
1024
UXGA
1600
1200
HDTV
1280
720
Digital image data is input at an input frame rate. An input frame rate is the rate at which a frame of data is received by the system. An output frame rate is the rate at which digital image data is provided to a display device for visually displaying the input image data. Common input and output frame rates include 60, 70, and 80 Hz.
Where the output frame rate and/or the resolution match the input frame rate and/or resolution, the frame of image data is be displayed directly without issue. If, however, the input and output frame rates and/or the resolutions differ substantially, the image data might not be properly displayed on the display device. This is particularly true in frame locked systems where small line memories are commonplace since these line memories do not allow for full frame rate conversion of the input frame rate to an output frame rate that matches the frame rate of the display device.
When the input and output frame rates differ, the display device and, more particularly, the software that drives the display device might enter an unrecoverable error mode. For example, assume UXGA image data input at 80 Hz and a VGA display running at 60 Hz. In this circumstance, the system is incapable of displaying the image data. The VGA display device might go blank except perhaps for a single line that reads SYNCH ERROR. A system reset will not generally cure the error because the image data will still be delivered at a frame rate and resolution combination that exceeds the capability of the display device. The software driving the display device will not give a perplexed user a way of changing its settings to ensure the error does not recur.
Accordingly, a need remains for a system including a failsafe mechanism adapted to visually display frame locked digital image data.
REFERENCES:
patent: 5473342 (1995-12-01), Tse et al.
patent: 5691768 (1997-11-01), Civanlar et al.
patent: 5991883 (1999-11-01), Atkinson
patent: 6359625 (2002-03-01), Perego
patent: 6466264 (2002-10-01), Shioji
LeVasseur Jamie J.
West Michael G.
Marger Johnson & McCollom PC
Patel Nitin
Pixelworks, Inc.
Shankar Vijay
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