Failsafe decision circuit

Details Failsafe decision circuit Failsafe decision circuit

1985-09-13

1986-04-15

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 328164, 375 4, 375108, H03K 501

Patent

active

045830070

ABSTRACT:
A decision circuit is responsive to digital input signals and to timing signals for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals required by a prior art decision circuit.

REFERENCES:
patent: 2942196 (1960-06-01), De Lange
patent: 3488526 (1970-01-01), Bohrer et al.
patent: 3518456 (1970-06-01), Mauduit et al.
"A Single Chip Regenerator for Transmission Systems Operating in the Range 2-320 Mbits/s", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 3, Jun. 1982, pp. 553-558.

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