Fail-safe zero delay buffer with automatic internal reference

Details Fail-safe zero delay buffer with automatic internal reference Fail-safe zero delay buffer with automatic internal reference

2001-08-13

2004-07-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06768362

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing zero delay buffers generally and, more particularly, to a method and/or architecture for a zero delay buffer featuring an automatic reference loop which generates an internal reference clock that may be phase aligned to an externally supplied reference clock. In the event the externally supplied reference clock stops, the automatic reference loop will continue to supply an internal reference clock.
BACKGROUND OF THE INVENTION
A signal buffer that inserts essentially no additional propagation delay in the signal path is required for many applications. A phase locked loop (PLL) or delay locked loop (DLL) based zero delay buffer can address the requirement for essentially no additional propagation delay. A continuous clock, even in the event of loss of a reference signal, is also required for many applications.
Conventional timing systems can result in problems, for example, when used in communications systems that derive timing from incoming data streams. Loss of the data stream (due to storm, interference, etc.) can result in loss of circuit timing generation unless a backup timing source is available.
Conventional timing circuits can use backup reference oscillators to compensate for the loss of the primary timing reference. Conventional backup reference oscillators have multiplexers with external control logic to select between the primary and secondary (backup) reference oscillator where both the primary and secondary reference oscillator are located “off-chip”. However, conventional technology has the following disadvantages: (i) external control circuitry is required to control the reference selection multiplexer, (ii) the secondary reference is not phase aligned with the primary reference, (iii) a change from the primary reference to the secondary reference and back can result in an interruption of the clock, and/or (iv) a secondary reference source is required.
It would be desirable to have a zero delay buffer circuit that (i) has a reference oscillator phase aligned with a primary reference oscillator and (ii) automatically provides an internal reference clock if the primary reference stops.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for a zero delay buffer with an automatic reference clock that may (i) simplify the design of clock systems, (ii) reduce or eliminate complicated decision making/control logic, (iii) reduce or eliminate multiplexers, (iv) eliminate “off chip” backup reference oscillators, (v) provide a phase aligned (e.g., phase coherent) reference oscillator that provides uninterrupted operation when a primary timing reference signal is lost, (vi) provide a smooth, continuous reference oscillator operation when the primary timing reference signal is restored, (vii) provide continuous clocking in the event of data derived clock loss, (viii) handle clock management/switching internally as part of the chip architecture, and/or (ix) insert negligible propagation path delay.


REFERENCES:
patent: 4615005 (1986-09-01), Maejima et al.
patent: 4633193 (1986-12-01), Scordo
patent: 4686386 (1987-08-01), Tadao
patent: 4787097 (1988-11-01), Rizzo
patent: 4851987 (1989-07-01), Day
patent: 5065047 (1991-11-01), Igari et al.
patent: 5120988 (1992-06-01), Matsuki
patent: 5136180 (1992-08-01), Caviasca et al.
patent: 5175845 (1992-12-01), Little
patent: 5223931 (1993-06-01), Fernsler et al.
patent: 5233931 (1993-08-01), McCorkle, Jr.
patent: 5260979 (1993-11-01), Parker et al.
patent: 5388265 (1995-02-01), Volk
patent: 5410572 (1995-04-01), Yoshida
patent: 5502689 (1996-03-01), Peterson et al.
patent: 5512860 (1996-04-01), Huscroft et al.
patent: 5541943 (1996-07-01), Niescier et al.
patent: 5552727 (1996-09-01), Nakao
patent: 5572167 (1996-11-01), Alder et al.
patent: 5577086 (1996-11-01), Fujimoto et al.
patent: 5634131 (1997-05-01), Matter et al.
patent: RE35797 (1998-05-01), Graham et al.
patent: 5828253 (1998-10-01), Murayama
patent: 5842029 (1998-11-01), Conary et al.
patent: 5935253 (1999-08-01), Conary et al.
patent: 6072345 (2000-06-01), Ooishi
patent: 6104251 (2000-08-01), Ramey et al.
patent: 6193422 (2001-02-01), Belt et al.
patent: 6229774 (2001-05-01), Yasuda
patent: 6236278 (2001-05-01), Olgaard
patent: 6236693 (2001-05-01), Haulin
patent: 6282210 (2001-08-01), Rapport et al.
patent: 6433599 (2002-08-01), Friedrich et al.

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