Fail-safe MOS shutdown circuitry

Details Fail-safe MOS shutdown circuitry Fail-safe MOS shutdown circuitry

1994-01-12

1996-11-12

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, H02H 900

Patent

active

055746098

ABSTRACT:
A dual discharge network is shown discharging any residual charge on the gates of MOSFET's used to protect a device from over voltages. The dual discharge networks are separately responsive to a positive or negative voltage at an input terminal such as an I/O input terminal, for example. Bias to each of the discharge networks is provided by the positive or negative I/O voltage and power to the transistors within each discharge network is provided by the MOSFET gate charges. In this way, a conduction path is formed between the positively and negatively charged MOSFET gates driving the gates towards ground, driving the MOSFETs to non-conduction and isolating a protected device from a I/O over-voltage where positive or negative.

REFERENCES:
patent: 3947727 (1976-03-01), Stewart
patent: 4860152 (1989-08-01), Osborn
patent: 5359211 (1994-10-01), Groft
patent: 5400202 (1995-03-01), Metz et al.

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