Fail-safe electronic time delay circuit

Details Fail-safe electronic time delay circuit Fail-safe electronic time delay circuit

1976-08-12

1977-08-23

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328129, 361196, 361203, H03K 513, H01H 4718

Patent

active

040442721

ABSTRACT:
This disclosure relates to a fail-safe time delay circuit for providing a definite time interval. The time delay circuit includes a resistance-capacitance charging network which is connected to a source of a d.c. supply source by a switching device. The potential charge developed on the capacitor powers an inverter to produce a.c. signals having a given frequency. The a.c. signal is fed to a multi-stage tuned amplifier having a resonant circuit tuned to the given frequency. The amplified a.c. signals are applied to a voltage doubling network which normally energizes a load and which maintains the load energized for no longer than the definite time interval after the opening of the switching device.

REFERENCES:
patent: 3407340 (1968-10-01), Hufnagel
patent: 3411020 (1968-11-01), Lake
patent: 3747014 (1973-07-01), Darrow
patent: 3873893 (1975-03-01), Bianchini
patent: 3955125 (1976-05-01), Butler et al.

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