Fail safe digital timer

Details Fail safe digital timer Fail safe digital timer

1980-11-28

1983-02-08

Malzahn, David H.

Excavating

371 58, 371 14, 377 29, G06F 1116

Patent

active

043732011

ABSTRACT:
A fail safe digital timer is provided by having a pair of similar counters counting the output of a single clock means. The clock means provides clock pulses and complimentary clock pulses to the two counters and the outputs of the counters are compared. If the two counters are properly operating the comparison will provide a continuous stream of pulses at a frequency equal to the frequency of the clock means for the timer. The failure of any of the components in the system cause the output of the comparator means to either become a constant logic 1 or a constant logic 0.

REFERENCES:
patent: 3155939 (1964-11-01), Vadus
patent: 3618015 (1971-11-01), Homonick
patent: 3845282 (1974-10-01), Mattson
patent: 3898444 (1975-08-01), Cordi et al.
patent: 4096396 (1978-06-01), Belforte et al.
patent: 4255809 (1981-03-01), Hillman

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