Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-07-13
2001-02-13
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S530000
Reexamination Certificate
active
06188271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential terminator which provides a fail safe bias for a bus having tri-state drivers, and, more particularly, the present invention is directed to a method and apparatus which uses current sources to provide fail safe bias voltages to the bus.
2. Background
In a computer system, various subsystems must communicate with each other. For instance, a memory subsystem and a central processor unit (CPU) subsystem exchange data. Similarly, the CPU subsystem exchanges data with I/O subsystems. Data exchanges within a computer system are commonly performed using one or more buses. In particular, a typical bus can be advantageously used as a shared communication link between subsystems. That is, multiple subsystems can transfer data on the bus at different times by applying signals to the bus which can be received by other subsystems on the bus.
When multiple subsystems share the same bus, only one subsystem generally applies signals to the bus at any particular time, and during that time, the other subsystems do not apply signals to the bus. Thus, although the other subsystems are connected to the shared bus, the bus transmitters (i.e., drivers) associated with the other subsystems are disabled such that only the bus transmitters associated with the subsystem applying signals to the bus are active.
A number of techniques can be used to implement a shared bus system. For example, the subsystems can use open-collector drivers or tri-state drivers. The present invention will be described below in connection with buses wherein the subsystems have transmitters which are tri-state drivers. Briefly, tri-state drivers have an enabled state and a disabled state. When a tri-state driver is enabled, the tri-state driver can apply a signal to a bus having a first drive level (e.g., a signal level corresponding to a logical one) or a second drive level (e.g., a signal level corresponding to a logical zero). Depending upon the type of bus, the first and second drive levels may be voltage levels with respect to a reference voltage (e.g., a logical one represented by a relatively high voltage with respect to logic ground and a logical zero represented by a relatively low voltage with respect to logic ground), or the first and second drive levels may be differential voltages between two driver outputs wherein the first drive level may be a differential voltage of a first relative polarity between the two driver outputs and the second drive level may be a differential voltage of a second relative polarity between the two driver outputs. When a tri-state driver is in a disabled state, the tri-state driver has substantially no effect on the bus. That is, the outputs of the disabled tri-state driver are effectively disconnected from the bus or are connected to the bus via very high impedances.
When data are being transferred on a shared bus, the various control and signal lines on the bus will have known states determined by the enabled tri-state drivers of the particular subsystem currently controlling the bus. However, when no subsystem is controlling the bus and no tri-state drivers are driving the various lines of the bus, the voltage levels on the control and signal lines of the bus may be unknown. For example, in an exemplary small computer systems interface (SCSI) bus, the protocol for controlling the SCSI bus includes a bus idle state wherein certain control and signal lines on the bus are not being driven by any subsystem connected to the SCSI bus. In other words, during the bus idle state, the control and signal lines are “floating” (i.e., the voltage levels on the lines or the relative voltages between differential lines are indeterminate).
Because the bus control and signal lines are floating during the bus idle state, noise may then make the bus more susceptible to a false transition where a receiver will perceive the noise as an assertion or deassertion of a control line, for example.
It is known to add bus terminators to the control and signal lines of a bus, such as a SCSI bus. Such terminators provide a fail safe bias which sets the voltage levels on the bus to a known state. A conventional way to provide a fail safe bias for differential signal buses is to use a three-resistor stack or voltage divider, as illustrated in FIG.
1
. The three resistors R
1
, R
2
, R
3
are connected in series between the highest (i.e., most positive) supply voltage and the lowest (e.g., logic ground or most negative) supply voltage. The fail safe bias voltage is provided by the voltage drop across the center resistor R
2
.
A disadvantage of generating the fail safe bias across the center resistor R
2
is that the voltage across the center resistor R
2
is directly related to source voltage Vcc (i.e., the most positive supply voltage with respect to the most negative supply voltage or ground). Because the voltage across the center resistor R
2
varies as Vcc changes, the bus is highly susceptible to noise from various devices connected to the bus. In addition, the fail safe bias resistors affect the equivalent output impedance of the terminator, hence further degrading the performance of the bus. Another disadvantage is that the conventional fail safe bias is not switchable (i.e., cannot be turned on and off) as a function of the transmission rate of the bus. This has been found by the inventors herein to be a problem because loading of the bus caused by the termination resistors may preclude high-speed operation of the bus.
SUMMARY OF THE INVENTION
The present invention provides a fail safe bias voltage for a bus which is not affected by the output impedance of a current source. The present invention also provides a fail safe bias which can be easily switched in and out depending on the transmission rate of the bus.
One embodiment of the present invention comprises a current source. A first resistor and a second resistor are connected in series between the current source and a current sink. The series connection of the two resistors is connected across a pair of differential bus lines to provide a passive termination impedance. A first switch electrically connects the current source to the first resistor and a second switch electrically connects the current sink to the second resistor.
When the first switch and the second switch are closed, current flows through the series connection of the two resistors to provide a bias voltage between the differential bus lines. The bias voltage is generated between first and second nodes. The first node is located between the current source and the first resistor.
The current source is switched to the first node. The second node is located between the current sink and the second resistor. The current sink is switched to the second node. A third node is located at a common connection between the first and second resistors. Preferably, a third bias impedance (e.g., a third resistor) is connected between the third node and a voltage source which provides a common mode bias voltage to the differential bus lines.
In another embodiment, a fail safe bias circuit selectively provides a bias voltage to a bus having a first signal line and a second signal line. The fail safe bias circuit comprises at least one resistor connected between the first signal line and the second signal line, a current source and a first switch interposed between the current source and the first signal line. The fail safe bias circuit further comprises a current sink; and a second switch which is connected between the current sink and the second signal line.
The first switch and the second switch are operable in respective first states to enable current to flow from the current source via the resistor to the current sink so as to generate a bias voltage between the first signal line and the second signal line. The first switch and the second switch are also operable in respective second states to interrupt current flow from the current source through the resistor.
In another embodiment, the resistor comprises
Wallace Dean A.
Wang Minhui
Kim Jung Ho
Knobbe Martens Olson & Bear LLP
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