Fail-operational fault tolerant flight critical computer archite

Details Fail-operational fault tolerant flight critical computer archite Fail-operational fault tolerant flight critical computer archite

1993-04-27

1996-08-27

Park, Collin W.

Boots, shoes, and leggings

364184, 244 76R, 318563, 371 681, G06F 1116

Patent

active

055507360

ABSTRACT:
A flight critical computer system for an aircraft includes dual independent lanes having two processors in each lane. The first lane has a primary processor and a redundant processor and provides a first command signal. The second lane includes a primary processor and a redundant processor and provides a second command signal. A first monitor compares the primary processor of the first lane with the primary processor of the second lane and generates first comparison signals as a function of disagreement therebetween. A second monitor compares the output signals of the redundant processor of the second lane and the primary processor of the first lane and generates second comparison signals as a function of disagreement therebetween. A third monitor compares the primary processor of the second lane with the redundant processor of the first lane and generates third comparison signals as a function of disagreement therebetween. Selection logic selects as a function of the first, second and third comparison signals at least output generated by the processors as a command signal of the system while allowing for at least one processor to fail before both command signals from the lanes, respectively, are disabled.

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