Factored nanoscale multiplexer/demultiplexer circuit for...

Details Factored nanoscale multiplexer/demultiplexer circuit for... Factored nanoscale multiplexer/demultiplexer circuit for...

2007-11-06

2007-11-06

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Multiplexing

C365S189020, C327S407000, C327S415000, C977S940000, C977S932000

Reexamination Certificate

active

11123551

ABSTRACT:
Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address lines needed for unique addressing in a deterministic, non-randomly fabricated multiplexer or demultiplexer are used. The number of address lines in excess of the minimal number of address lines needed for unique addressing in a deterministic multiplexer or demultiplexer are referred to as supplemental address lines. The number of supplemental address lines needed for a randomly fabricated nanoscale multiplexer or demultiplexer can be decreased by employing two stages within the multiplexer or demultiplexer, the first stage having deterministically fabricated interconnections between signal lines and a first set of address lines, and the second stage having randomly fabricated interconnections between signal lines and a second set of address lines.

REFERENCES:
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 6314019 (2001-11-01), Kuekes et al.
patent: 6559468 (2003-05-01), Kuekes et al.
patent: 6952358 (2005-10-01), Snider
Millman et al., Microelectronics, 2nd Ed., McGraw-Hill, 1987, pp. 283-286.

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