Facility for reducing a data rate

Details Facility for reducing a data rate Facility for reducing a data rate

1998-07-02

2000-12-19

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708316, G06F 1717, G06F 1710

Patent

active

061637874

ABSTRACT:
A facility for reducing the data rate of a data sequence (d1) is provided, including a switchable filter device (1) which delivers first output values (dn) after a sampling intervals in a first state and second output values (dm) after a +1 sampling intervals in a second state, and which has at least one tracking data window (dw) of different sizes (dwf1, dwf2) for forming filtered data values (df'). A control device (10) causes n first output values (dn) and m second output values (dm) to be formed within equally long time periods (I2) of the data sequence (d1), with the number of n first and m second output values being determined by a rule r=a+m/(n+m), where r is a desired data rate reduction factor.

REFERENCES:
patent: 4999798 (1991-03-01), McCaslin et al.
patent: 5528527 (1996-06-01), Iwata et al.
patent: 5619438 (1997-04-01), Farley et al.
patent: 5694345 (1997-12-01), Peterson
patent: 5777908 (1998-07-01), Inogai
patent: 5777911 (1998-07-01), Sherry et al.
patent: 5831879 (1998-11-01), Yom et al.

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