Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
2011-05-10
2011-05-10
Fennema, Robert (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
Reexamination Certificate
active
07941638
ABSTRACT:
One embodiment of the present invention provides a system that performs a fast-scanning operation to generate fetch bundles within an instruction fetch unit (IFU) of a processor. During operation, the system obtains a cache line containing instructions at the IFU. Next, the system performs a complete-scanning operation on the cache line to identify control transfer instructions (CTIs) in the cache line. At the same time, the system performs a fast-scanning operation to identify CTIs in a group of initial instructions in the cache line, wherein the initial instructions are executed before other instructions in the cache line. Next, the system obtains results from the fast-scanning operation before results of the complete-scanning operation are available. The system then uses results from the fast-scanning operation to form an initial fetch bundle containing initial instructions, and sends the initial fetch bundle to the instruction-issue unit.
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patent: 2005/0033941 (2005-02-01), Joyce et al.
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patent: 2006/0242365 (2006-10-01), Ali et al.
Shen, John Paul, Lipasti, Mikko. “Modern Processor Design: Fundamentals of Superscalar Processors”. McGraw-Hill, 2005. pp. 230-231.
Dictionary.com: “subset” definition. 2009.
Ali Abid
Ewoldt Andrew T.
Fennema Robert
Oracle America Inc.
Park Vaughan Fleming & Dowler LLP
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