Active solid-state devices (e.g. – transistors – solid-state diode – With specified impurity concentration gradient – With high resistivity
Reexamination Certificate
1999-09-30
2001-10-16
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With specified impurity concentration gradient
With high resistivity
C257S653000
Reexamination Certificate
active
06303979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a diode device, having both electrodes provided on a same surface thereof, capable of being directly connected to a conductive pattern on a circuit board without using lead wires.
2. Description of the Related Arts
Face-down bonding is a method for directly attaching integrated circuits to circuit boards such as printed boards and the like without using lead wires, conventionally used in the construction of various types of electronic circuits.
According to this method, electrodes are provided on the same surface of the integrated circuit, which is then turned face down and bonded directly to the circuit board. Since the integrated circuit consequently requires no packaging, the size of the integrated circuit can be scaled-down, lowering costs. For these reasons, face-down bonding is widely used.
However, although this method can be used for integrated circuits, chiefly provided with transistors, in which electrodes can be disposed on the same surface, it has not been possible to use face-down bonding in the case of diode devices having only two electrodes, such as, for instance, variable-capacity diodes.
FIG. 4
is a cross-sectional view illustrating a conventional variable-capacity diode device, in which region
3
and region
4
, having different conductive types, are provided within an epitaxial layer
2
on a silicon semiconductor substrate
1
, thereby forming a PN junction such as super abrupt junction.
In
FIG. 4
,
5
is an insulating film comprising silicon oxide,
6
is an electrode connecting to region
4
,
15
is a lead wire,
16
and
17
are board-shaped terminals formed from lead frames.
Region
4
is exposed on the surface of the semiconductor main body which comprises the substrate
1
and the epitaxial layer
2
, enabling an electrode to be provided on the surface of region
4
. But, since region
3
lies beneath region
4
, an electrode
18
, which connects to region
3
, is provided on the underside of the substrate
1
.
The underside electrode
18
is securely joined to the terminal
16
, by inserting a gold ribbon into the joint interface between the substrate
1
and the terminal
16
and applying heat thereto, a eutectic bond being formed of the terminal
16
, the gold ribbon and the substrate.
The surface electrode
6
is connected to the terminal
17
by a gold lead wire
15
.
The terminals
16
and
17
only are exposed to the outside, and packaging, such as a resin sealant, is provided. The terminals
16
and
17
are then connected to a circuit board.
Thus it has not been possible to connect the conventional diode device to a circuit board by means of face-down bonding since the two electrodes cannot be provided on the same surface.
SUMMARY OF THE INVENTION
The present invention aims to provide a diode device, having both electrodes provided on the same surface thereof, which can be face-down bonded to a circuit board.
In order to achieve the above objective, the face down bonding PIN diode of the present invention comprises: a semiconductor main body; a first region of a conductivity type, said first region being provided within a semiconductor main body, a surface of said first region being exposed at the first surface of said semiconductor substrate; a third region of a conductivity type opposite that of said first region, said third region being provided within said semiconductor so as to be positioned under said first region; a fifth region of substantially intrinsic semiconductor, said fifth region being positioned between said first region and said third region so as to form junctions on said first region and said third region, respectively; a fourth region of the same conductivity type, said fourth region being provided within said semiconductor main body, a surface of said fourth region being exposed at the first surface of said semiconductor main body and extended vertically from said first surface to said third surface; a first electrode provided on a predetermined surface of said semiconductor main body so as to be connected to said first region; and a second electrode provided on the predetermined surface of said semiconductor, said second electrode being connected to said fourth region and connected to said third region through said fourth region.
Since a region at one end of the diode to form the diode junction is provided within the semiconductor main body, it is not possible to connect an electrode to this region at the surface of this region. Therefore, another region, which has the same conductivity type as the region provided within the semiconductor main body, is exposed at the surface, so as to enable the electrode to be connected at the surface via this other region.
REFERENCES:
patent: 3821779 (1974-06-01), Usuda
patent: 4250520 (1981-02-01), Denlinger
patent: 4608589 (1986-08-01), Goth et al.
patent: 4860083 (1989-08-01), Kojo
patent: 4999683 (1991-03-01), Kiyomura et al.
patent: 5144406 (1992-09-01), Hemings et al.
patent: 5181083 (1993-01-01), Pezzani
Flynn Nathan
Pillsbury & Winthrop LLP
Toko Kabushiki Kaisha
Wilson Scott R.
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