Fabrication technique for junction devices

Details Fabrication technique for junction devices Fabrication technique for junction devices

1980-08-18

1983-01-25

Lusignan, Michael R.

Coating processes

Electrical product produced

Superconductor

427 99, 427250, 427251, 4272552, 4272555, 4272557, 204192D, B05D 512

Patent

active

043703593

ABSTRACT:
A self-aligning technique is used to produce small area junctions such as small area Josephson junctions. A base layer having a thickness corresponding to one dimension of the junction is first deposited. An insulating material is then deposited from a source positioned so that the base layer itself masks its edge from the insulator being formed. This procedure coats the base layer with an insulator, but leaves an edge of this layer free of insulation. A junction is then completed on this uncoated edge.

REFERENCES:
patent: 3205087 (1965-09-01), Allen
patent: 3288637 (1966-11-01), Ames
patent: 3725213 (1973-04-01), Pierce
patent: 3908263 (1975-09-01), Matarese
patent: 4176029 (1979-11-01), Jillie
patent: 4218532 (1980-08-01), Dunkleberger
Vossen et al., Thin Film Processes, pp. 175-176, 193, Academic Press Inc., N. Y., N. Y. .COPYRGT.1978.
Dolan, Applied Physics Letters, vol. 31, No. 5, pp. 337-339, Sep. 1977.
Greiner et al., IBM J. Res. and Dev., 24, 195 (1980).
Daalmans et al., Alternatives in Fabricating Submicron Niobium Josephson Junctions, American Institute of Physics Conference Proceedings, No. 44, 1978.

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