Fabrication technique for integrated circuits

Details Fabrication technique for integrated circuits Fabrication technique for integrated circuits

1984-08-03

1986-03-25

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29590, 29591, 156643, 156653, 156647, 1566591, 148DIG19, H01L 21283, H01L 2128, H01L 2156

Patent

active

045773920

ABSTRACT:
A method is set forth for forming conductive contacts to first, second and third regions of a substrate. The substrate is covered with an insulating layer having a slot with an island therein. The island is covered with a first sacrificial layer. The substrate is covered with a conformal coating of a dielectric material. The coating is etched off with retention of sacrificial portions of the dielectric material between the island and the insulating layer. The first sacrificial layer is removed from the island while the sacrificial portions remain. A conductive layer is deposited upon the substrate. A second sacrificial layer is laid down upon the conductive layer. The second sacrificial layer is etched away along with the sacrificial portions of the dielectric material while the conductive layer is not significantly removed. Highly conductive contacts are provided with the conductive material self-aligned on the source, drain and gate.

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IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sep. 81, pp. 1970-1973, "Self-Aligned Silicide Conductors in FET IC" Osburn et al.
IEEE IEDM 81-647 "An Optimally Designed Process for Submicron MOSFETS" T. Shibata et al.
IBM Technical Disclosure Bulletin, vol. 27, No. 2, Jul. 1984, pp. 1044-1045 "Salicide with Buried Silicide Layer" Jones et al.
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