Fabrication process of sub-micrometer channel length MOSFETs

Details Fabrication process of sub-micrometer channel length MOSFETs Fabrication process of sub-micrometer channel length MOSFETs

1981-12-30

1983-12-13

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29591, 148 15, 148187, H01L 21265

Patent

active

044198094

ABSTRACT:
Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

REFERENCES:
patent: 3648125 (1972-03-01), Peltzer
patent: 4062699 (1977-12-01), Armstrong
patent: 4089992 (1978-05-01), Doo et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4201603 (1980-05-01), Scott, Jr. et al.
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4209349 (1980-06-01), Ho et al.
patent: 4209350 (1980-06-01), Ho et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4256514 (1981-03-01), Pogge
patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4287661 (1981-09-01), Stoffel
patent: 4294002 (1981-10-01), Jambotkar et al.
patent: 4322883 (1982-04-01), Abbas et al.
patent: 4358340 (1982-11-01), Fu
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4364166 (1982-12-01), Crowder et al.
patent: 4374700 (1983-02-01), Scott et al.
H. B. Pogge, IBM Technical Disclosure Bulletin, "Narrow Line-Width Masking Method", Nov. 1976, vol. 19, No. 6, pp. 2057-2058.
S. A. Abbas et al., IBM Technical Disclosure Bulletin, "Extending the Minimal Dimensions of Photolithographic . . . ", Sep. 1977, vol. 20, No. 4, pp. 1376-1378.
"A New Edge-defined Approach for Sub-micrometer MOSFET Fabrication" by W. R. Hunter et al., IEEE Electron Device Letters, vol. EDL-2, No. 1, Jan. 1981, pp. 4-6.
"Sub-micrometer Polysilicon Gate CMOS/SOS Technology" by A. C. Ipri et al., IEEE Transactions on Electron Devices, vol. ED-27, No. 7, Jul. 1980, pp. 1275-1279.
"A Novel Sub-micron Fabrication Technique" by T. N. Jackson et al., IEDM 1979, Conference vol., pp. 58-61.
"A New Short Channel MOS FET with Lightly Doped Drain" by Saito et al., in Denshi Tsushin Rengo Taikai, (Japanese), Apr. 1978, pp. 2-20.

Affiliated with

Also associated with

Rating

Fabrication process of sub-micrometer channel length MOSFETs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication process of sub-micrometer channel length MOSFETs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication process of sub-micrometer channel length MOSFETs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-799247