Fabrication process of a stack type semiconductor capacitive ele

Details Fabrication process of a stack type semiconductor capacitive ele Fabrication process of a stack type semiconductor capacitive ele

1997-05-09

1999-01-12

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, 438398, H01L 2120

Patent

active

058588523

ABSTRACT:
At first, a silicon oxide layer is selectively formed on the surface of a semiconductor substrate. Next, a first amorphous silicon film doped with phosphorous in the concentration of about 1.times.10.sup.20 (atoms/cm.sup.3) and a non-doped second amorphous silicon film are deposited in sequential order. By this, an amorphous silicon layer for lower electrode constituted of the first and second amorphous silicon films is formed. Then, an HSG (unevenness) is formed on the surface of the amorphous silicon layer for lower electrode. Subsequently, the amorphous silicon layer for lower electrode is patterned to form a lower electrode of the stack type capacitive element. Thereafter, a capacitance insulation layer is formed on the upper surface and the side surface of the lower electrode. Then, over the entire surface, an upper electrode is deposited.

REFERENCES:
patent: 5418180 (1995-05-01), Brown
patent: 5639689 (1997-06-01), Woo
patent: 5663085 (1997-09-01), Tanigawa
Japanese Office Action, mailed Mar. 3, 1998, in corresponding JPA No. 8114637/1996 (translation of relevancy submitted herewith).

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