Fabrication process of a semiconductor device having a reduced p

Details Fabrication process of a semiconductor device having a reduced p Fabrication process of a semiconductor device having a reduced p

1992-03-06

1993-12-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 46, 148DIG9, H01L 21225

Patent

active

052702499

ABSTRACT:
A fabrication process of a semiconductor device comprises the steps of providing a temporary layer on a semiconductor substrate, patterning the temporary layer to form a temporary protection pattern on the semiconductor substrate such that the temporary protection pattern has a pair of opposing side walls extending generally vertically, relatively to the semiconductor substrate, forming a first conductor layer, having incorporated therein an impurity element of a first conductivity type, so as to bury the temporary protection pattern therebeneath, patterning the first conductor layer to form a pair of first type conductor regions contiguous the respective, opposing side walls of the temporary protection pattern, removing the temporary protection pattern selectively with respect to the first type conductor regions thereby to leave the pair of first type conductor regions on the substrate, forming a second conductor layer such that the second conductor layer buries the first type conductor regions therebeneath, patterning the second conductor layer such that only a region thereof remains between the pair of first type conductor regions, as a second type conductor region, and forming first diffusion regions in the substrate respectively in correspondence to the first type conductor regions by diffusion thereinto of the first conductivity type impurity element from the pair of first type conductor regions.

REFERENCES:
patent: 4808548 (1989-02-01), Thomas et al.
patent: 4868137 (1989-09-01), Kubota
patent: 4963502 (1990-10-01), Teng et al.
patent: 5030584 (1991-07-01), Nakata
patent: 5100813 (1992-03-01), Nihira et al.

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