Fabrication process for wafer alignment marks by using periphera

Details Fabrication process for wafer alignment marks by using periphera Fabrication process for wafer alignment marks by using periphera

1991-07-19

1992-07-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437924, 437947, 148 334, 148DIG50, H01L 21441

Patent

active

051282801

ABSTRACT:
A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.

REFERENCES:
patent: 4534804 (1985-08-01), Cade
patent: 4636281 (1987-01-01), Buiguez et al.
patent: 4824795 (1989-04-01), Blanchard
patent: 4936930 (1990-06-01), Gruber et al.

Affiliated with

Also associated with

Rating

Fabrication process for wafer alignment marks by using periphera does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication process for wafer alignment marks by using periphera, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication process for wafer alignment marks by using periphera will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1829508