Fabrication process for programmable and erasable MOS memory dev

Details Fabrication process for programmable and erasable MOS memory dev Fabrication process for programmable and erasable MOS memory dev

1992-11-10

1995-11-21

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437195, H01L 218247

Patent

active

RE0350940

ABSTRACT:
An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window. The window is filled with a thin oxide layer and the floating gate is formed so that its edge lies over a portion of the window. Control gates, sources and drains are formed last.

REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.
patent: 4119995 (1978-10-01), Simko
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4558344 (1985-12-01), Perlegos
patent: 4598460 (1986-07-01), Owens et al.
patent: 4608585 (1986-08-01), Keshtbood
patent: 4642881 (1987-02-01), Matsukawa
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4727043 (1988-02-01), Matsumoto et al.
patent: 4745083 (1988-05-01), Huie
patent: 4794562 (1988-12-01), Kato et al.
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4878199 (1989-10-01), Mizutani
J. D. Plummer, "Process Physics; Implications for Manufacturing of Submicron Silicon Devices", Solid State Technology, Mar. 1986, pp. 61-66.

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