Fabrication process for multilevel interconnections in a semicon

Details Fabrication process for multilevel interconnections in a semicon Fabrication process for multilevel interconnections in a semicon

1995-02-24

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437231, 437228, 437982, H01L 2144

Patent

active

055061770

ABSTRACT:
After forming lower level wiring and plasma oxide layer, SOG film is applied by applying a solution containing hydrogen silsesquioxane as primary component under rotation. Pre-baking of the SOG film is performed by a first heat treatment and causes reflow thereof by a second heat treatment at a temperature higher than the first heat treatment. Subsequently, another plasma oxide layer is formed. By this, in an interlayer insulation layer including SOG film, occurrence of crack and so forth can be prevented and water resistance can be improved.

REFERENCES:
patent: 5145723 (1992-09-01), Ballance et al.
Ballance, David S., et al., "Low Temperature Reflow Planarization Using a Novel Spin-On Interlevel Dielectric", Jun. 9-10, 1992 VMIC Conference, 1992 ISMIC-101/92/0180, pp. 180-188.

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