Fabrication process for IC circuit and IC circuits fabricated th

Details Fabrication process for IC circuit and IC circuits fabricated th Fabrication process for IC circuit and IC circuits fabricated th

1991-11-29

1993-06-29

Pascal, Robert J.

Wave transmission lines and networks

Plural channel systems

333238, H01P 500, H01P 308

Patent

active

052238040

ABSTRACT:
A method of minimizing line capacitance for transmission lines in integrated circuits is presented to decrease the device performance problems of time delay and noise generation caused by capacitive coupling effects. The prime objective is to decrease the high line capacitance associated with such long length lines as clock lines, buslines and analogue signal lines as well as designated lines requiring low line capacitance. A procedure for applying CAD to such a design concept is also indicated. Although the present embodiments refer to transmission lines within one layer of an IC, the basic concept outlined is applicable also to multilayer designs.

REFERENCES:
patent: 4383227 (1983-05-01), de Ronde
patent: 4675620 (1987-06-01), Fullerton
patent: 4680557 (1987-07-01), Compton
patent: 5027088 (1991-06-01), Shimizu et al.

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