Fabrication process for EEPROMS with high voltage transistors

Details Fabrication process for EEPROMS with high voltage transistors Fabrication process for EEPROMS with high voltage transistors

1988-02-04

1989-07-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 52, 437 57, 437 58, 357 235, H01L 21265, H01L 2978, H01L 2994, H01L 2996

Patent

active

048513610

ABSTRACT:
A CMOS fabrication process for EEPROMs having high-breakdown-voltage peripheral transistors in which a single implant step early in the process forms buried implants for both the memory cell's tunnel area source and the high voltage transistor's source and drain areas. The single implant step can be formed either before or after the formation of the channel stops and field oxide around the devices. The floating gate of the memory cell and the gates of the other devices are formed with polysilicon, the gates of the high voltage transistor overlapping the buried implants of its source and drain. The sources and drains of the other peripheral devices are then formed, using their polysilicon gates as a self-aligning mask. This may also include the formation of contact source and drain for the high voltage transistor. The process concludes with the formation of one or two layers of conductive lines connecting to specified drains, sources and gates to form a desired circuit pattern.

REFERENCES:
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Ken Yu et al., "HMOS-CMOS--A Low-Power High-Performance Technology", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct., 1981, pp. 454-459.

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