Fabrication process for compound semiconductor device

Details Fabrication process for compound semiconductor device Fabrication process for compound semiconductor device

1995-08-17

1996-05-07

Thomas, Tom

Fishing, trapping, and vermin destroying

437 56, 437133, 437912, H01L 218232

Patent

active

055146058

ABSTRACT:
On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.

REFERENCES:
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patent: 4733283 (1988-03-01), Kuroda
patent: 5021857 (1991-06-01), Suehiro
patent: 5104825 (1992-04-01), Takikawa
patent: 5356823 (1994-10-01), Mitani
patent: 5409849 (1995-04-01), Kishita et al.
patent: 5411903 (1995-05-01), Wu et al.
H. Suehiro, et al., "A New Recessed-Gate Structure for Short-Gate HEMT ICs", Japan Electronic Information Communication Engineering Institute, vol. 89, No. 366, ED89-133, 1990, pp. 29-34.

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