Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Forming lateral transistor structure
Reexamination Certificate
1999-08-30
2001-07-03
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Forming lateral transistor structure
C438S339000, C438S361000, C438S364000
Reexamination Certificate
active
06255184
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a bipolar transistor device, featuring a three dimensional trench emitter region.
(2) Description of Prior Art
Although complimentary metal oxide semiconductor, (CMOS), devices have been extensively used to fabricate integrated circuits, bipolar devices, exhibiting faster switching speeds than CMOS devices, are now being used to increase the performance of bipolar-CMOS, (BiCMOS), designs, when compared to counterpart designs entailing only CMOS devices. In addition advances in bipolar configurations, such as emitter regions obtained from diffusion from overlying polysilicon emitter structures, compared to conventional emitter regions, obtained via ion implantation, directly into the semiconductor substrate, have allowed improved bipolar devices to be realized. For example the depth of emitter regions, formed from polysilicon emitter structures, can be maintained at narrower levels than emitter regions obtained via direct ion implantation procedures. This is a result of the absence of ion implantation channelling, and as a result of the elimination of a post-ion implant anneal, sometimes resulting in excessive drive-in of the emitter, into the base region. Therefore the use of the more controllable polysilicon emitter structure, has allowed the attainment of narrower base widths, which in results in higher performing bipolar device, in terms of frequency response, (Ft).
The emitter resistance is in part, a function of the level of interface area between the emitter, and underlying base region. However increasing the interface area directly increases the dimensions of the bipolar device, adversely influencing the objective of device miniaturization. This invention will describe the fabrication of a bipolar device, featuring a trench, polysilicon emitter structure, maximizing interface area while minimizing device area. In addition this invention will describe a novel procedure used to fabricate a narrow base region, along the sides of the emitter trench region. Prior art, such as Chambers et al, in U.S. Pat. No. 5,488,003, as well as Chambers et al, in U.S. No. 5,856,697, describe procedures used to create polysilicon emitter structures, located in a trench, however these prior arts do not teach the novel procedure described in this present invention, of forming narrow base widths, along the sides of the emitter trench, prior to the polysilicon filling of the emitter trench.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a bipolar device featuring a three dimensional, trench, polysilicon emitter structure.
It is another object of this invention to form a narrow width base region, along the sides of an emitter trench, prior to formation of the trench, polysilicon emitter structure.
In accordance with the present invention a method of fabricating a bipolar junction transistor, featuring a three dimensional, polysilicon emitter trench structure, and featuring a narrow width base region, formed along the sides of the emitter trench, prior to the formation of the polysilicon emitter structure, is described. After creation of deep trench isolation regions, in the semiconductor substrate, and creation of field oxide, isolation regions, in an N type epitaxial silicon layer, an emitter trench is formed in the N type epitaxial layer, in a first region of the semiconductor substrate, located between two field oxide regions. A P type, base region is next formed in the exposed regions N type epitaxial silicon layer, in a first region of the semiconductor substrate, including formation of the P type, base region in the region of the semiconductor substrate located along the sides of the emitter trench. An N type, polysilicon emitter structure is next defined, overlying the region of the P type, base region, located along the sides of the emitter trench. An anneal cycle is then used to diffuse N type dopant from the N type, polysilicon emitter structure, into a top portion of P type base region, resulting in a narrow width, P type base region, comprised of the uncompensated region of the P type, base region. After creation of insulator spacers, on the sides of the portion of the N type, polysilicon emitter structures, not located in the emitter trench, diffused, P type contact regions, are formed, placed in a region of the semiconductor substrate, located between the field oxide regions, and the insulator spacers. P type, polysilicon contact structures are then formed overlying the P type, contact regions, as well as overlying the field oxide regions, located adjacent to the emitter trench. After deposition of, and planarization of, a dielectric layer, contact openings are made in the dielectric layer, exposing a portion of the top surface of the N type, polysilicon emitter structure, as well as exposing a portion of the top surface of a P type, polysilicon contact structure. Another trench region, used for a collector trench, is also formed in the dielectric layer, and in a second region of the semiconductor substrate, located between another set of field oxide regions. Metal contact structures are then formed, resulting in: a base contact structure, overlying and contacting the P type, polysilicon contact structure; an emitter contact structure, overlying and contacting the N type, polysilicon emitter structure; and resulting in a collector contact structure, located in the opening in the dielectric layer, and in the collector trench, overlying and contacting a buried N type subcollector layer, located underlying the N type epitaxial layer.
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Ackerman Stephen B.
Episil Technologies Inc.
Saile George O.
Trinh Michael
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