Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
1999-04-19
2001-01-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S350000, C438S364000, C438S365000
Reexamination Certificate
active
06180478
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a bipolar junction transistor, (BJT), on a semiconductor substrate.
(2) Description of Prior Art
Bipolar junction transistors, offering enhanced performance when compared to metal oxide semiconductor field effect transistor, (MOSFET), devices, have been used to improve the performance of bipolar-complementary MOS, (BiCMOS), chips, specifically chips used for microprocessor applications. The enhanced performance of BJT devices, is a result of a faster switching frequency, offered via reductions in the base width of the BJT device. In addition reductions in RC delays, accomplished via the use conductive extrinsic base layers, as well as accomplished via capacitance reductions, in turn obtained via the use of micro-miniaturization processing of specific regions of the BJT device, have also allowed increased BJT performance to be realized.
This invention will describe a fabrication process for a BJT device in which only a single polysilicon layer is used, for the emitter level, while extrinsic base, and intrinsic base regions, are formed in an epitaxial silicon base layer, deposited on underlying silicon seed layer, and on an underlying N type, epitaxial layer, with the intrinsic base region either formed in an undoped, epitaxial silicon base layer, or contained in the deposited epitaxial silicon base layer. These features result in a reduction in BJT area, specifically the reduction of base-collector, as well as collector-substrate capacitance, thus reducing performance degrading RC delays. This invention will also describe procedures in which the epitaxial silicon base layer is a composite epitaxial layer, used for the intrinsic base region, comprised of either a boron doped, silicon layer, or a boron doped, silicon-germanium layer, which increases transistor switching frequency, (Ft), again resulting in enhanced performance. Prior art, such as Solheim, in U.S. Pat. No. 5,071,778, describes a process for improving the device characteristics of a BJT device, via a self-aligned collector implant. However that prior art does not describe the unique processing features used in this invention, resulting in improved BJT performance, such as an epitaxial silicon layer, providing for both an extrinsic and intrinsic base region.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a BJT device, in which RC delays are reduced as a result of reducing junction capacitance.
It is another object of this invention to reduce junction capacitance via a reduction in the area of base-collector, and collector to substrate, regions.
It is still another object of this invention to use only a single polysilicon layer, for the emitter structure, while an epitaxial silicon layer is deposited in an active device region, providing the material for the accommodation of an extrinsic base region, as well as for the intrinsic base region, thus reducing the active device region of the BJT, as well as junction capacitance, when compared to counterpart BJT devices, fabricated with double polysilicon layers.
It is yet another object of this invention to either ion implant an intrinsic base region, into an epitaxial silicon layer, or to provide an epitaxial silicon region, deposited with the intrinsic base region.
In accordance with the present invention a method of fabricating a bipolar junction transistor, (BJT), has been developed, featuring reduced junction capacitance, via reductions in the area of the active device region, and enhanced device performance, accomplished via the use of a epitaxial grown layer, formed on the active device region, providing for both the extrinsic and intrinsic base regions. After formation of an N+ subcollector region, and of P well, buried layer isolation regions, in a P type semiconductor substrate, an N type, epitaxial silicon layer is deposited. After formation of a collector reach through region, as well as field oxide, (FOX), isolation regions, a silicon seed layer, comprised of either amorphous silicon, or polysilicon, is formed on the surface of the FOX regions, and extending to overlay a portion of the active device region, located between FOX regions. An epitaxial silicon base layer is deposited on the underlying silicon seed layer, as well as on the underlying N type, epitaxial silicon layer, exposed in the active device region. The epitaxial silicon base layer can be deposited intrinsically, requiring a first photolithographic and ion implantation procedure, to convert a first portion of the epitaxial silicon base region, to a P type, extrinsic base region, followed by a second photolithographic and ion implantation procedure, used to convert a second portion of the epitaxial silicon base layer to a P type, intrinsic base region, in an area directly overlying the active device region. The photolithographic and ion implantation procedures, used to create the intrinsic base regions, can however be omitted via deposition of an epitaxial silicon base layer, already containing either the specific level of P type dopant, needed for the intrinsic base region, or containing the specific level of P type dopant, in addition to a specific level of germanium, needed for an enhanced, P type, intrinsic base region. After opening an emitter contact hole, in an insulator layer, exposing a portion of the top surface of the intrinsic base region, an N type, polysilicon emitter structure is formed. An anneal cycle is next performed to allow N type diffusion from the overlying N type polysilicon emitter structure, to form a shallow emitter region, in the top portion of the P type, intrinsic base region, exposed in the emitter contact hole, resulting in a P type, intrinsic base region, located between the overlying, diffused emitter region, and the underlying collector region, or the N type, epitaxial silicon layer. Deposition of a thick insulator layer, and opening of contact holes in the thick insulator layer: to the N type, polysilicon emitter structure; to the P type, extrinsic base region; and to the collector reach through region; is followed by formation of metal contact structure, located in the contact holes, contacting the underlying emitter, base, and collector regions.
REFERENCES:
patent: 5071778 (1991-12-01), Solheim
patent: 5592017 (1997-01-01), Johnson
patent: 5593905 (1997-01-01), Johnson et al.
patent: 5736447 (1998-04-01), Choi et al.
patent: 5773350 (1998-06-01), Herbert et al.
patent: 5786622 (1998-07-01), Ronkainen
patent: 5869380 (1999-02-01), Chang
Huang Tzuen-Hsi
Lee Chwan-Ying
Liou Tsyr-Shyang
Ackerman Stephen B.
Industrial Technology Research Institute
Le Dung A
Nelms David
Saile George O.
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